PIC18F4321-I/PT Microchip Technology, PIC18F4321-I/PT Datasheet
PIC18F4321-I/PT
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PIC18F4321-I/PT Summary of contents
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... Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2007 Microchip Technology Inc. PIC18F4321 Family Data Sheet 28/40/44-Pin Preliminary DS39689E ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4321 8K 4096 © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Peripheral Highlights (Continued): • Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI (all 4 modes) and I Master and Slave modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN 1.2 ...
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... PIC18F4321 FAMILY Pin Diagrams 28-Pin SPDIP, SOIC, SSOP MCLR/V RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL Note 1: RB3 is the alternate pin for CCP2 multiplexing. 28-Pin QFN RA2/AN2/V REF- RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 Note 1: RB3 is the alternate pin for CCP2 multiplexing. ...
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... RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 Note 1: RB3 is the alternate pin for CCP2 multiplexing. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY /RE3 REF 37 + REF ...
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... PIC18F4321 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 379 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 379 Index ................................................................................................................................................................................................. 381 The Microchip Web Site ..................................................................................................................................................................... 391 Customer Change Notification Service .............................................................................................................................................. 391 Customer Support .............................................................................................................................................................................. 391 Reader Response .............................................................................................................................................................................. 392 PIC18F2221/2321/4221/4321 Product Identification System ............................................................................................................ 393 © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 5 ...
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... PIC18F4321 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Microchip Technology Inc. PIC18F4321 FAMILY 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F4321 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. • ...
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... DS39689E-page 8 1.3 Details on Individual Family Members Devices in the PIC18F4321 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1 ...
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... Resets (and Delays) RESET Instruction, Stack Underflow MCLR (optional), Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Packages © 2007 Microchip Technology Inc. PIC18F4321 FAMILY PIC18F2221 PIC18F2321 DC – 40 MHz DC – 40 MHz 4096 8192 2048 4096 512 512 256 ...
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... PIC18F4321 FAMILY FIGURE 1-1: PIC18F2221/2321 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (4 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine ...
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... OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Data Bus<8> Data Latch 8 Data Memory (3 ...
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... PIC18F4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS Pin Number SPDIP, Pin Name SOIC, QFN SSOP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 9 6 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... with I C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... PIC18F4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RB0/INT0/FLT0/AN12 21 18 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 22 19 RB1 INT1 AN10 RB2/INT2/AN8 23 20 RB2 INT2 AN8 RB3/AN9/CCP2 24 21 RB3 AN9 (2) CCP2 RB4/KBI0/AN11 25 22 RB4 ...
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... with I C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 32 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... PIC18F4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/INT0/FLT0/AN12 33 9 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 34 10 RB1 INT1 AN10 RB2/INT2/AN8 35 11 RB2 INT2 AN8 RB3/AN9/CCP2 36 12 RB3 AN9 (2) CCP2 RB4/KBI0/AN11 37 14 RB4 KBI0 ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0/PSP0 19 38 RD0 PSP0 RD1/PSP1 20 39 RD1 PSP1 RD2/PSP2 21 40 RD2 PSP2 RD3/PSP3 22 41 RD3 PSP3 RD4/PSP4 27 2 RD4 PSP4 RD5/PSP5/P1B 28 3 RD5 PSP5 P1B ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features (44-Pin TQFP Packages Only)” for more information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 22 Preliminary © 2007 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F4321 family of devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F4321 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR QUARTZ CRYSTALS Typical Capacitor Values Crystal Tested: Osc Type Freq kHz MHz MHz MHz MHz MHz MHz 22 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test ...
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... EXT 20 pF ≤ C ≤ 300 pF EXT © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... PIC18F4321 FAMILY 2.6 Internal Oscillator Block The PIC18F4321 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... Minimum frequency Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift affect the controller operation in a variety of ways possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register ...
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... PIC18F4321 FAMILY 2.6.5.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F4321 family of devices are shown in Figure 2-11. See Section 23.0 “Special Features of the CPU” for Configuration register details. ...
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... Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS The PIC18F4321 family of devices contains circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... Modifying the SCSI:SCSO bits will cause an immediate clock source switch. 5: Modifying the IRCF3:IRCF0 bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY (1) R/W-0 R/W-0 R (5) (5) ...
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... PIC18F4321 FAMILY 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the configured oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin in Crystal Oscillator modes) will stop oscillating. ...
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... POWER-MANAGED MODES PIC18F4321 family devices offer a total of seven oper- ating modes for more efficient power-management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • ...
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... PIC18F4321 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY n-1 n (1) ...
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... PIC18F4321 FAMILY If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
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... Sleep Mode The power-managed Sleep mode in the PIC18F4321 family devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared ...
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... PIC18F4321 FAMILY 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution ...
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... PIC18F4321 FAMILY 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT HSPLL modes ...
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... RESET The PIC18F4321 family devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F4321 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 IPEN SBOREN bit 7 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit If BOREN1:BOREN0 = 01 BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00 11: Bit is disabled and read as ‘ ...
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... The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F4321 family devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” ...
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... PIC18F4321 FAMILY 4.4 Brown-out Reset (BOR) PIC18F4321 family devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configu- ration bits. There are a total of four BOR configurations which are summarized in Table 4-1. ...
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... Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F4321 family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms. ...
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... PIC18F4321 FAMILY FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F4321 FAMILY , V RISE > PWRT T OST T PWRT T OST T PLL ...
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... PIC18F4321 FAMILY 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F4321 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices FSR1H 2221 2321 4221 4321 FSR1L 2221 2321 4221 4321 BSR 2221 2321 4221 4321 INDF2 2221 2321 4221 4321 POSTINC2 2221 2321 4221 4321 POSTDEC2 2221 2321 4221 4321 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F4321 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR2 2221 2321 4221 4321 PIR2 2221 2321 4221 4321 PIE2 2221 2321 4221 4321 IPR1 2221 2321 4221 4321 2221 2321 4221 4321 PIR1 2221 2321 4221 4321 ...
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... Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM Memory”. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F4321 FAMILY DEVICES PIC18FX221 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 • ...
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... PIC18F4321 FAMILY 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs ...
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... PIC18F4321 FAMILY 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... PIC18F4321 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
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... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F4321 family devices implement 2 banks. Figure 5-5 shows the data memory organization for the PIC18F4321 family devices ...
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... PIC18F4321 FAMILY FIGURE 5-5: DATA MEMORY MAP FOR PIC18F4321 FAMILY DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh = 0001 Bank 1 = 0010 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39689E-page 60 Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh Unused Read ‘ ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 7 Data Memory 1 000h ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F4321 FAMILY DEVICES Address Name Address FFFh ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 4 Bit 3 Bit 2 Bit 1 Top-of-Stack Upper Byte (TOS< ...
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... PIC18F4321 FAMILY TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — — (1) RCON ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 4 Bit 3 Bit 2 Bit 1 ...
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... PIC18F4321 FAMILY 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruc- tion that affects the Z, DC bits, the results of the instruction are not written ...
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... Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘ ...
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... PIC18F4321 FAMILY 5.4.3.1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
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... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM ...
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... PIC18F4321 FAMILY FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When ‘a’ and ‘f’ ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is inter- ...
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... F80h by using the BSR. FFFh © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 72 Preliminary © 2007 Microchip Technology Inc. ...
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... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F4321 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 R/W-x R/W-0 — FREE ...
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... PIC18F4321 FAMILY 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER ...
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... MOVF TABLAT, W MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F4321 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F4321 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
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... WREN to enable byte writes. 8. Disable interrupts. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. ...
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... PIC18F4321 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVFW TABLAT MOVWF POSTINC0 DECFSZ COUNTER GOTO ...
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... OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 82 Preliminary © 2007 Microchip Technology Inc. ...
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... EEPROM. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
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... PIC18F4321 FAMILY REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers ...
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... BSF INTCON, GIE BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
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... PIC18F4321 FAMILY 7.5 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 “ ...
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... IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — FREE WRERR WREN — ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 88 Preliminary © 2007 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F4321 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: ...
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... PIC18F4321 FAMILY Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • 2 ...
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... INTERRUPTS The PIC18F4321 family devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h ...
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... PIC18F4321 FAMILY FIGURE 9-1: PIC18 INTERRUPT LOGIC SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39689E-page 92 TMR0IF ...
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... Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
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... PIC18F4321 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 R/W-0 U-0 — ...
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... PIC18F4321 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 R/W-0 R/W-0 — EEIF BCLIF HLVDIF W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 100
... PIC18F4321 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-0 R/W-0 R/W-0 — EEIE BCLIE HLVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PIC18F4321 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY U-0 R/W-1 R/W-1 R/W-1 — EEIP BCLIP HLVDIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 104
... PIC18F4321 FAMILY 9.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 9-10: RCON: RESET CONTROL REGISTER ...
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... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 104 Preliminary © 2007 Microchip Technology Inc. ...
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... PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch (LATA) register is also memory mapped. ...
Page 108
... PIC18F4321 FAMILY TABLE 10-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/ RA2 0 V -/CV REF REF 1 AN2 REF CV REF x RA3/AN3/V + RA3 REF 0 1 AN3 REF 1 RA4/T0CKI/C1OUT RA4 0 1 T0CKI 1 C1OUT 0 RA5/AN4/SS/ RA5 0 HLVDIN/C2OUT ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F4321 FAMILY 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY I/O I/O Type O DIG LATB< ...
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... PIC18F4321 FAMILY TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB PORTB Data Latch Register (Read and Write to Data Latch) TRISB PORTB Data Direction Control Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 ...
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... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
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... PIC18F4321 FAMILY TABLE 10-5: PORTC I/O SUMMARY TRIS Pin Function Setting RC0/T1OSO/ RC0 0 T13CKI 1 T1OSO x T13CKI 1 RC1/T1OSI/CCP2 RC1 0 1 T1OSI x (1) CCP2 0 1 RC2/CCP1/P1A RC2 0 1 CCP1 0 1 (2) P1A 0 RC3/SCK/SCL RC3 0 1 SCK 0 1 SCL 0 1 RC4/SDI/SDA RC4 0 1 SDI 1 SDA ...
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... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary Reset Bit 1 ...
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... PIC18F4321 FAMILY 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on 40/44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... P1D 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY I/O I/O Type O DIG LATD<0> data output. ...
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... PIC18F4321 FAMILY TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 PORTD RD7 RD6 LATD PORTD Data Latch Register (Read and Write to Data Latch) TRISD PORTD Data Direction Control Register TRISE IBF OBF CCP1CON P1M1 P1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. ...
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... PORTE, TRISE and LATE Registers Depending on the particular PIC18F4321 family device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as analog inputs, these pins will read as ‘ ...
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... PIC18F4321 FAMILY REGISTER 10-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 IBF OBF bit 7 bit 7 IBF: Input Buffer Full Status bit word has been received and waiting to be read by the CPU word has been received bit 6 OBF: Output Buffer Full Status bit ...
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... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY I/O I/O Type O DIG LATE< ...
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... PIC18F4321 FAMILY 10.6 Parallel Slave Port Note: The Parallel Slave Port is only available on 40/44-pin devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1) ...
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... IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 122 Preliminary © 2007 Microchip Technology Inc. ...
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... Prescale value Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
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... PIC18F4321 FAMILY 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 126 Preliminary © 2007 Microchip Technology Inc. ...
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... Stops Timer1 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F4321 FAMILY 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
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... T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F4321 FAMILY 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
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... Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 132 Preliminary © 2007 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
Page 136
... PIC18F4321 FAMILY 13.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit output counter/ postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... Stops Timer3 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 138
... PIC18F4321 FAMILY 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 14-1: TIMER3 BLOCK DIAGRAM (8-BIT READ/WRITE MODE) Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger CCP1/CCP2 Select from T3CON<6,3> ...
Page 139
... T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F4321 FAMILY NOTES: DS39689E-page 138 Preliminary © 2007 Microchip Technology Inc. ...
Page 141
... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F4321 family devices all have two CCP (Capture/Compare/PWM) modules. Each module con- tains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter ...
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... PIC18F4321 FAMILY 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
Page 143
... Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... PIC18F4321 FAMILY 15.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
Page 145
... The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F4321 FAMILY 15.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCP2CON register will force ...
Page 147
... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY EQUATION 15-3: PWM Resolution (max) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared ...
Page 148
... PIC18F4321 FAMILY TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) PIR1 PSPIF ADIF (2) PIE1 PSPIE ADIE (2) IPR1 PSPIP ADIP TRISB PORTB Data Direction Control Register TRISC PORTC Data Direction Control Register TMR2 ...
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... PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of the ECCP module are the same as described for the standard CCP module ...
Page 150
... PIC18F4321 FAMILY In addition to the expanded range of modes available through the CCP1CON and ECCP1AS registers, the ECCP module has an additional register associated with Enhanced PWM operation and auto-shutdown features; it is: • ECCP1DEL (Dead-band delay) 16.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode ...
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... PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation ...
Page 152
... PIC18F4321 FAMILY 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation ...
Page 153
... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 16.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay 0 ...
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... PIC18F4321 FAMILY 16.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 156
... PIC18F4321 FAMILY FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F4X21 P1A P1B P1C P1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows user to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
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... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F4321 FAMILY (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period t1 ...
Page 158
... PIC18F4321 FAMILY 16.4.6 PROGRAMMABLE DEAD-BAND DELAY Note: Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules. In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power ...
Page 159
... Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Unimplemented on 28-pin devices; bits read as ‘0’. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 ( Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 160
... PIC18F4321 FAMILY 16.4.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 161
... Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 162
... PIC18F4321 FAMILY TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) PIR1 PSPIF ADIF (2) PIE1 PSPIE ADIE (2) IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISB PORTB Data Direction Control Register ...
Page 163
... SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four SPI modes are supported. To accomplish communication, typically three pins are used: • ...
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... PIC18F4321 FAMILY 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented C™ mode only. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 OSC ...
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... PIC18F4321 FAMILY 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers ...
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... PIC18F4321 FAMILY 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI operation is only going to receive, the SDO output could be disabled (programmed as an input) ...
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... Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F4321 FAMILY SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...
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... PIC18F4321 FAMILY FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
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... PIC18F4321 FAMILY 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
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... In Receive mode SSPBUF is full (does not include the ACK and Stop bits SSPBUF is empty (does not include the ACK and Stop bits) Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2 C™ MODE) R-0 R-0 R-0 CKE ...
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... PIC18F4321 FAMILY REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I transmission to be started (must be cleared in software collision In Slave Transmit mode: ...
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... In Slave mode (7-bit Address mode Address masking of ADD1 enabled 0 = Address masking of ADD1 disabled In Slave mode (10-bit Address mode Address masking of ADD1 and ADD0 enabled 0 = Address masking of ADD1 and ADD0 disabled © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 2 C™ MODE) R/W-0 R/W-0 R/W-0 (1) ...
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... PIC18F4321 FAMILY REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I R/W-0 R/W-0 GCEN ACKSTAT bit 7 bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware Start condition Idle In Slave mode Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) ...
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... I C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register ...
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... PIC18F4321 FAMILY 17.4.3.2 Address Masking Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an inter- rupt possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to ...
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... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.4.3.4 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F4321 FAMILY 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39689E-page 178 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 179 ...
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... PIC18F4321 FAMILY 2 FIGURE 17-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39689E-page 180 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-11: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK = 01001 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 181 ...
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... PIC18F4321 FAMILY 2 FIGURE 17-12: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39689E-page 182 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 183 ...
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... PIC18F4321 FAMILY 17.4.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
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... DX SCL CKP WR SSPCON © 2007 Microchip Technology Inc. PIC18F4321 FAMILY already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-14) ...
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... PIC18F4321 FAMILY 2 FIGURE 17-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39689E-page 186 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-16: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 187 ...
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... PIC18F4321 FAMILY 17.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
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... FIGURE 17-18: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and ...
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... PIC18F4321 FAMILY 2 17.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
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... C™ interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
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... PIC18F4321 FAMILY 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high ...
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... FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the SCL line is sampled low before the SDA ...
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... PIC18F4321 FAMILY 2 17.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD< ...
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... This may result in a corrupted transfer. The user should verify that the WCOL flag is clear after each write to SSPBUF to ensure the transfer is correct. © 2007 Microchip Technology Inc. PIC18F4321 FAMILY 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
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... PIC18F4321 FAMILY 2 FIGURE 17-23: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39689E-page 196 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 17-24: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F4321 FAMILY Preliminary DS39689E-page 197 ...
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... PIC18F4321 FAMILY 17.4.12 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to gen- erate an Acknowledge, then the ACKDT bit should be cleared ...