PIC18F4321-I/PT Microchip Technology, PIC18F4321-I/PT Datasheet - Page 317

• Manufacturer Part Number: PIC18F4321-I/PT
• Description: IC PIC MCU FLASH 4KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4321-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.2
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F4321 family devices also
provide an optional extension to the core CPU function-
ality. The added features include eight additional
instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Offset Addressing mode for many of the
standard PIC18 instructions.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set (with the exception
of CALLW, MOVSF and MOVSS) can all be classified as
literal operations, which either manipulate the File
Select Registers, or use them for indexed addressing.
Two of the instructions, ADDFSR and SUBFSR, each
have an additional special instantiation for using FSR2.
These versions (ADDULNK and SUBULNK) allow for
automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and deallocation of software
• function pointer invocation
• software Stack Pointer manipulation
• manipulation of variables located in a software
TABLE 24-3:
© 2007 Microchip Technology Inc.
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
stack space when entering and leaving
subroutines
stack
Mnemonic,
Operands
Extended Instruction Set
f, k
k
z
z
k
f, k
k
s
s
, f
, z
d
EXTENSIONS TO THE PIC18 INSTRUCTION SET
d
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move z
Move z
Store literal at FSR2,
Subtract literal from FSR
Subtract literal from FSR2 and
decrement FSR2
return
f
z
d
s
s
d
(destination)2nd word
(source) to 1st word
(source) to 1st word
(destination)2nd word
Description
Preliminary
Cycles
1
2
2
2
2
1
1
2
A summary of the instructions in the extended instruction
set is provided in Table 24-3. Detailed descriptions are
provided in Section 24.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 24-1
(page 274) apply to both the standard and extended
PIC18 instruction sets.
24.2.1
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byte-
oriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 24.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
PIC18F4321 FAMILY
Note:
Note:
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
MSb
16-Bit Instruction Word
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be
generated by a compiler.
EXTENDED INSTRUCTION SYNTAX
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text
arguments are denoted by braces (“{ }”).
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
reviewing
and
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
ffkk
11kk
0001
going
code
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
LSb
forward,
DS39689E-page 315
that
Affected
Status
has
None
None
None
None
None
None
None
None
optional
been