PIC18F4321-I/PT Microchip Technology, PIC18F4321-I/PT Datasheet - Page 221

• Manufacturer Part Number: PIC18F4321-I/PT
• Description: IC PIC MCU FLASH 4KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4321-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 18-6:
FIGURE 18-7:
TABLE 18-6:
© 2007 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing
the OERR (overrun) bit to be set.
These bits are unimplemented on 28-pin devices and read as ‘0’.
RX
BRG16
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
EUSART RECEIVE BLOCK DIAGRAM
ASYNCHRONOUS RECEPTION, TXCKP = 0 (TX NOT INVERTED)
Start
bit
SPBRGH
Baud Rate Generator
x64 Baud Rate CLK
RXDTP
bit 0
RCIDL
and Control
ADIF
ADIE
ADIP
Pin Buffer
Bit 6
RX9
TX9
bit 1
SPBRG
SPEN
TMR0IE
RXDTP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
bit 7/8
Recovery
Preliminary
Interrupt
÷ 64
÷ 16
÷ 4
Data
TXCKP
Stop
INT0IE
CREN
SYNC
or
or
bit
Bit 4
TXIF
TXIE
TXIP
Word 1
RCREG
CREN
Start
bit
ADDEN
SENDB
bit 0
BRG16
SSPIE
SSPIP
SSPIF
RBIE
PIC18F4321 FAMILY
Bit 3
RX9
Stop
MSb
RCIF
RCIE
RX9D
TMR0IF
CCP1IF
CCP1IE
CCP1IP
bit 7/8
BRGH
FERR
Word 2
RCREG
(8)
Bit 2
—
OERR
7
Stop
bit
RSR Register
RCREG Register
• • •
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
8
Start
WUE
Bit 1
bit
Data Bus
1
FERR
0
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
Bit 0
RBIF
DS39689E-page 219
bit 7/8
LSb
Start
FIFO
Stop
bit
on page
Values
Reset
49
52
52
52
51
51
51
51
51
51