PIC24FJ32GB002-I/SO Microchip Technology, PIC24FJ32GB002-I/SO Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ32GB002-I/SO
• Description: IC MCU 16BIT 32KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GB002-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240019, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

voltage supply designs: one supply for the core and
regulator. The specifications for core voltage and capac-
PIC24FJ64GA1/GB0
2.1
All devices in the PIC24FJ64GA1/GB0 families are dual
peripherals, and another for the I/O pins. A regulator is
provided on-chip to alleviate the need for two external
voltage supplies.
All PIC24FJ64GA1/GB0 devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the PIC24FJ64GA1/GB0 families
incorporate an on-chip regulator that allows the device
to run its core logic from V
The regulator provides power to the core from the other
V
be connected to the V
Figure 2-2). This helps to maintain the stability of the
itance are listed in Section 7.0 “AC/DC Characteristics
and Timing Requirements”.
2.2
The Flash program memory on PIC24FJ64GA1/GB0
devices has a specific write/erase requirement that
must be adhered to for proper device operation. The
rule is that any given word in memory must not be writ-
ten more than twice before erasing the page in which it
is located. Thus, the easiest way to conform to this rule
is to write all the data in a programming block within
one write cycle. The programming methods specified in
this specification comply with this requirement.
2.3
The pin diagrams for the PIC24FJ64GA1/GB0 families
are shown in Figure 2-3 through Figure 2-6. The pins
that are required for programming are listed in
Table 2-1 and are shown in bold letters in the figures.
Refer to the appropriate device data sheet for complete
pin descriptions.
2.3.1
All of the devices in the PIC24FJ64GA1/GB0 families
have three separate pairs of programming pins,
labelled as PGEC1/PGED1, PGEC2/PGED2 and
PGEC3/PGED3. Any one of these pin pairs may be
used for device programming by either ICSP or
Enhanced ICSP. Unlike voltage supply and ground
pins, it is not necessary to connect all three pin pairs to
program the device. However, the programming
method must use both pins of the same pair.
DS39934B-page 2
DD
Note:
pins. A low-ESR capacitor (such as tantalum) must
Power Requirements
Program Memory Write/Erase
Requirements
Pin Diagrams
Writing to a location multiple times without
erasing is not recommended.
PGCx AND PGDx PIN PAIRS
DDCORE
DD
.
pin (Table 2-1 and
FIGURE 2-2:
Regulator Enabled (DISVREG tied to V
Regulator Disabled (DISVREG tied to V
Regulator Disabled (V
Note 1: These are typical operating voltages. Refer
(10 μF typ)
2.5V
2.5V
C
EFC
to Section 7.0 “AC/DC Characteristics and
Timing Requirements” for the full operating
ranges of V
(1)
(1)
3.3V
3.3V
(1)
DD
CONNECTIONS FOR THE
ON-CHIP REGULATOR
© 2009 Microchip Technology Inc.
DD
and V
V
DISVREG
V
V
PIC24FJXXGA1/GB0
PIC24FJXXGA1/GB0
DD
DDCORE
SS
PIC24FJXXGA1/GB0
V
DISVREG
V
V
V
DISVREG
V
V
tied to V
DD
DDCORE
SS
DD
DDCORE
SS
DDCORE
/V
/V
DDCORE
/V
CAP
CAP
CAP
.
SS
DD
):
):
):