PIC24FJ32GB002-I/SO Microchip Technology, PIC24FJ32GB002-I/SO Datasheet - Page 22

• Manufacturer Part Number: PIC24FJ32GB002-I/SO
• Description: IC MCU 16BIT 32KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GB002-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240019, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA1/GB0
3.10
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
The verify process is shown in the flowchart in
Figure 3-8. Memory reads occur a single byte at a time,
so two bytes must be read to compare against the word
in the programmer’s buffer. Refer to Section 3.8
“Reading Code Memory” for implementation details
of reading code memory.
FIGURE 3-8:
DS39934B-page 22
Note:
Verify Code Memory and
Configuration Word
No
Because
include the device code protection bit, code
memory should be verified immediately
after writing if code protection is enabled.
This is because the device will not be read-
able or verifiable if a device Reset occurs
after the code-protect bit in CW1 has been
cleared.
with Post-Increment
with Post-Increment
Set TBLPTR = 0
Read High Byte
Read Low Byte
Word = Expect
code memory
verified?
Data?
Does
Done
Start
VERIFY CODE
MEMORY FLOW
the
All
Yes
Yes
Configuration
No
Failure,
Report
Error
registers
3.11
The Application ID Word is stored at address,
8007F0h, in executive code memory. To read this
memory location, you must use the SIX control code to
move this program memory location to the VISI
register. Then, the REGOUT control code must be
used to clock the contents of the VISI register out of the
device. The corresponding control and instruction
codes that must be serially transmitted to the device to
perform this operation are shown in Table 3-10.
After the programmer has clocked out the Application
ID Word, it must be inspected. If the Application ID has
the value, CBh, the programming executive is resident
in memory and the device can be programmed using
the mechanism described in Section 4.0 “Device
Programming – Enhanced ICSP”. However, if the
Application ID has any other value, the programming
executive is not resident in memory; it must be loaded
to memory before the device can be programmed. The
procedure for loading the programming executive to
memory is described in Section 5.4 “Programming
the Programming Executive to Memory”.
3.12
Exiting Program/Verify mode is done by removing V
from MCLR, as shown in Figure 3-9. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and program signals on PGCx
and PGDx before removing V
FIGURE 3-9:
MCLR
V
PGDx
PGCx
DD
Reading the Application ID Word
Exiting ICSP Mode
PGD = Input
EXITING ICSP™ MODE
© 2009 Microchip Technology Inc.
V
P16
IH
IH
.
P17
V
IH
IH