PIC24FJ32GB002-I/SO Microchip Technology, PIC24FJ32GB002-I/SO Datasheet - Page 32

• Manufacturer Part Number: PIC24FJ32GB002-I/SO
• Description: IC MCU 16BIT 32KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GB002-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240019, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA1/GB0
4.6.4
PIC24FJ64GA1/GB0 family devices provide two com-
plimentary methods to protect application code from
overwrites and erasures. These also help to protect the
device from inadvertent configuration changes during
run time. Additional information is available in the
product data sheet.
4.6.4.1
For all devices in the PIC24FJ64GA1/GB0 families, the
on-chip program memory space is treated as a single
block, known as the General Segment (GS). Code pro-
tection for this block is controlled by one Configuration
bit, GCP. This bit inhibits external reads and writes to
the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
4.6.4.2
In addition to global General Segment protection, a
separate subrange of the program memory space can
be individually protected against writes and erases.
This area can be used for many purposes where a
separate block of write and erase-protected code is
needed, such as bootloader applications. Unlike
common boot block implementations, the specially
protected segment in PIC24FJ64GA1/GB0 devices
can be located by the user anywhere in the program
space, and configured in a wide range of sizes.
DS39934B-page 32
CODE-PROTECT CONFIGURATION
BITS
GENERAL SEGMENT
PROTECTION
CODE SEGMENT PROTECTION
Code segment protection provides an added level of
protection to a designated area of program memory by
disabling the NVM safety interlock whenever a write or
erase address falls within a specified range. It does not
override General Segment protection controlled by the
GCP or GWRP bits. For example, if GCP and GWRP
are enabled, enabling segmented code protection for
the bottom half of program memory does not undo
General Segment protection for the top half.
4.7
Exiting Program/Verify mode is done by removing V
from MCLR, as shown in Figure 4-6. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and program signals on PGCx
and PGDx before removing V
FIGURE 4-6:
Note:
MCLR
V
PGDx
PGCx
DD
Exiting Enhanced ICSP Mode
Bulk Erasing in ICSP mode is the only way
to reprogram code-protect bits from an ON
state (‘0’) to an OFF state (‘1’).
PGDx = Input
EXITING ENHANCED
ICSP™ MODE
© 2009 Microchip Technology Inc.
V
P16
IH
IH
.
P17
V
IH
IH