PIC18LF2331-I/SO Microchip Technology, PIC18LF2331-I/SO Datasheet - Page 20

• Manufacturer Part Number: PIC18LF2331-I/SO
• Description: IC MCU FLASH 4KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2331-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18F2331/2431/4331/4431
3.5
The boot block segment is programmed in exactly the
same manner as the ID locations (see Section 3.4).
Multi-panel writes must be disabled so that only
addresses in the range 0000h to 01FFh will be written.
The code sequence detailed in Table 3-7 should be
used, except that the address data used in “Step 2” will
be in the range 000000h to 0001FFh.
TABLE 3-8:
FIGURE 3-9:
DS30500B-page 20
Step 1: Direct access to config memory.
Step 2: Position the program counter
Step 3
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
4-Bit
(2)
2:
: Set table pointer for config byte to be written. Write even/odd addresses.
Boot Block Programming
If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table write. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 100000h).
Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
bits. Always write all the configuration bits before enabling the write protection for configuration bits.
8E A6
8C A6
EF 00
F8 00
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
CONFIGURATION PROGRAMMING FLOW
Data Payload
Delay P9 Time
Configuration
Load Even
for Write
Program
Address
Done
Start
LSB
(1)
.
BSF
BSF
GOTO
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold SCLK high for time P9
EECON1, EEPGD
EECON1, CFGS
100000h
programmed a byte at a time. The “Table Write, Begin
3.6
Unlike code memory, the configuration bits are
Programming” 4-bit command (1111) is used but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses,
and the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is shown in Table 3-8.
Core Instruction
Configuration Bits Programming
Delay P9 Time
Configuration
Load Odd
for Write
Program
Address
Done
MSB
Start
 2010 Microchip Technology Inc.