PIC18LF2331-I/SO Microchip Technology, PIC18LF2331-I/SO Datasheet - Page 6

• Manufacturer Part Number: PIC18LF2331-I/SO
• Description: IC MCU FLASH 4KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2331-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18F2331/2431/4331/4431
In addition to the code memory space, there are three
blocks in the configuration and ID space that are acces-
sible to the user through table reads and table writes.
Their locations in the memory map are shown in
Figure 2-5.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the configuration bits. These bits select various device
options and are described in Section 5.0. These
configuration bits read out normally even after code
protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed
and are described in Section 5.0. These device ID bits
read out normally even after code protection.
FIGURE 2-5:
DS30500B-page 6
2FFFFFh
Note:
000000h
01FFFFh
1FFFFFh
3FFFFFh
Sizes of memory areas are not to scale.
Unimplemented
Code Memory
Configuration
Read as ‘0’
and ID
Space
CONFIGURATION AND ID LOCATIONS FOR PIC18FXX31 DEVICES
2.3.1
Memory in the address space 0000000h to 3FFFFFh is
addressed via the table pointer which is comprised of
three pointer registers:
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the table pointer prior to using many read or write
operations.
Addr[21:16]
TBLPTRU
MEMORY ADDRESS POINTER
Addr[15:8]
ID Location 1
ID Location 2
ID Location 3
ID Location 4
ID Location 5
ID Location 6
ID Location 7
ID Location 8
TBLPTRH
CONFIG1H
CONFIG2H
CONFIG3H
CONFIG4H
CONFIG5H
CONFIG6H
CONFIG7H
CONFIG1L
CONFIG2L
CONFIG3L
CONFIG4L
CONFIG5L
CONFIG6L
CONFIG7L
Device ID1
Device ID2
 2010 Microchip Technology Inc.
3FFFFEh
3FFFFFh
30000Ah
30000Bh
30000Ch
30000Dh
200000h
200001h
200002h
200003h
200004h
200005h
200006h
200007h
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
300008h
300009h
TBLPTRL
Addr[7:0]