PIC18LF2331-I/SO Microchip Technology, PIC18LF2331-I/SO Datasheet - Page 29

• Manufacturer Part Number: PIC18LF2331-I/SO
• Description: IC MCU FLASH 4KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2331-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TABLE 5-4:
 2010 Microchip Technology Inc.
WINEN
WDPS<3:0>
WDTEN
GPTREN
HPOL
LPOL
PWMPIN
Note 1:
Bit Name
(1)
(1)
2:
3:
4:
5:
(2)
Polarity control bits HPOL and LPOL define PWM signal output active and inactive states, PWM states
generated by the fault inputs or PWM manual override.
PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices.
When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices)
and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is
defined by HPOL and LPOL.
This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’).
For PIC18FX431 devices only.
PIC18FXX31 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG2H
CONFIG2H
CONFIG2H
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG3L
Words
Watchdog Timer Window Enable bit
1 = Enable window comparison
0 = Disable window comparison
Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit in WDTCON register)
GPT Reset upon CAP1 Special Event Trigger bit
1 = Special Event Reset enable (RESEN in TMR5CON register) is inactive.
0 = Special Event Reset enable (RESEN in TMR5CON register) is active and
High Side Transistors Polarity bit (i.e., Odd PWM Output Polarity Control bit )
1 = PWM 1, 3, 5, and 7 are active high (default)
0 = PWM 1, 3, 5, and 7 are active low
Low Side Transistors Polarity bit (i.e., Even PWM Output Polarity Control bit)
1 = PWM 0, 2, 4, and 6 are active high (default)
0 = PWM 0, 2, 4, and 6 are active low
PWM Output Pins RESET State Control bit
1 = PWM outputs disabled upon RESET (default)
0 = PWM outputs drive active states upon RESET
can enable the special event trigger signal from IC1 to reset the TMR5 time
base.
PIC18F2331/2431/4331/4431
Description
(3)
DS30500B-page 29