DSPIC33FJ64GS406-I/MR Microchip Technology, DSPIC33FJ64GS406-I/MR Datasheet - Page 320

• Manufacturer Part Number: DSPIC33FJ64GS406-I/MR
• Description: IC MCU/DSP 64KB FLASH 64QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS406-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-VQFN
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SCI, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 58
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 22-8:
DS70591C-page 320
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-8
Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
IRQEN5
IRQEN4
R/W-0
R/W-0
are in progress, the conversion will be performed when the conversion resources are available.
IRQEN5: Interrupt Request Enable 5 bit
1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed
0 = IRQ is not generated
PEND5: Pending Conversion Status 5 bit
1 = Conversion of channels AN11 and AN10 is pending; set when selected trigger is asserted
0 = Conversion is complete
SWTRG5: Software Trigger 5 bit
1 = Start conversion of AN11 and AN10 (if selected in TRGSRC bits)
This bit is automatically cleared by hardware when the PEND5 bit is set.
0 = Conversion is not started
TRGSRC5<4:0>: Trigger 5 Source Selection bits
Selects trigger source for conversion of analog channels AN11 and AN10.
00000 = No conversion enabled
00001 = Individual software trigger selected
00010 = Global software trigger selected
00011 = PWM Special Event Trigger selected
00100 = PWM Generator 1 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01011 = PWM Generator 8 primary trigger selected
01100 = Timer1 period match
01101 = PWM secondary special event trigger selected
01110 = PWM Generator 1 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10110 = PWM Generator 9 secondary trigger selected
10111 = PWM Generator 1 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11110 = PWM Generator 8 current-limit ADC trigger
11111 = Timer2 period match
PEND5
PEND4
R/W-0
R/W-0
ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
SWTRG5
SWTRG4
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
TRGSRC5<4:0>
TRGSRC4<4:0>
R/W-0
R/W-0
(1)
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0