PIC24FJ128GA106-I/PT Microchip Technology, PIC24FJ128GA106-I/PT Datasheet - Page 18

• Manufacturer Part Number: PIC24FJ128GA106-I/PT
• Description: IC PIC MCU FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA106-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GA
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GA110 FAMILY
TABLE 1-4:
DS39905E-page 18
CTED1
CTED2
CTPLS
CV
ENVREG
INT0
MCLR
OSCI
OSCO
PGEC1
PGED1
PGEC2
PGED2
PGEC3
PGED3
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMCS1
PMCS2
PMBE
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMRD
PMWR
Legend:
Function
REF
TTL = TTL input buffer
ANA = Analog level input/output
TQFP, QFN
64-Pin
28
27
29
23
57
35
39
40
15
16
17
18
11
12
30
29
16
22
32
31
28
27
24
23
45
44
51
60
61
62
63
64
53
52
7
8
6
5
4
1
2
3
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
80-Pin
TQFP
34
33
35
29
71
45
49
50
19
20
21
22
15
16
36
35
10
24
23
40
39
34
33
30
29
57
56
63
76
77
78
79
80
67
66
9
8
7
6
1
2
3
100-Pin
TQFP
100
42
41
43
34
86
55
13
63
64
24
25
26
27
20
21
44
43
14
12
11
10
29
28
50
49
42
41
35
34
71
70
78
93
94
98
99
82
81
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
Buffer
Input
ANA
ANA
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST = Schmitt Trigger input buffer
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C™ = I
CTMU External Edge Input 1.
CTMU External Edge Input 2.
CTMU Pulse Output.
Comparator Voltage Reference Output.
Voltage Regulator Enable.
External Interrupt Input.
Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
Main Oscillator Input Connection.
Main Oscillator Output Connection.
In-Circuit Debugger/Emulator/ICSP™ Programming Clock.
In-Circuit Debugger/Emulator/ICSP Programming Data.
In-Circuit Debugger/Emulator/ICSP Programming Clock.
In-Circuit Debugger/Emulator/ICSP Programming Data.
In-Circuit Debugger/Emulator/ICSP Programming Clock.
In-Circuit Debugger/Emulator/ICSP Programming Data.
Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
Parallel Master Port Address (Demultiplexed Master
modes).
Parallel Master Port Chip Select 1 Strobe/Address Bit 15.
Parallel Master Port Chip Select 2 Strobe/Address Bit 14.
Parallel Master Port Byte Enable Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
2
C/SMBus input buffer
Description
 2010 Microchip Technology Inc.