PIC24FJ128GA106-I/PT Microchip Technology, PIC24FJ128GA106-I/PT Datasheet - Page 67

• Manufacturer Part Number: PIC24FJ128GA106-I/PT
• Description: IC PIC MCU FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA106-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GA
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 6-1:
6.1
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to
further details.
TABLE 6-2:
 2010 Microchip Technology Inc.
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note:
Reset Type
WDTO
MCLR
SWR
POR
BOR
Clock Source Selection at Reset
Section 8.0 “Oscillator Configuration”
All Reset flag bits may be set or cleared by the user software.
Flag Bit
FNOSC Configuration bits
(CW2<10:8>)
COSC Control bits
(OSCCON<14:12>)
RESET FLAG BIT OPERATION
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
Trap Conflict Event
Illegal Opcode or Uninitialized W Register Access
Configuration Mismatch Reset
MCLR Reset
RESET Instruction
WDT Time-out
PWRSAV #SLEEP Instruction
PWRSAV #IDLE Instruction
POR, BOR
POR
Table
6-2. If clock
PIC24FJ256GA110 FAMILY
Setting Event
for
6.2
The Reset times for various types of device Reset are
summarized in
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Device Reset Times
Table
6-3. Note that the system Reset
PWRSAV Instruction, POR,
Clearing Event
CLRWDT
POR
POR
POR
POR
POR
POR
POR
DS39905E-page 67
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