ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet - Page 271

• Manufacturer Part Number: ATMEGA16-16PU
• Description: IC AVR MCU 16K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parallel Programming
Characteristics
2466R–AVR–06/08
Figure 133. Parallel Programming Timing, Including some General Timing Requirements
Figure 134. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
(DATA, XA0/1, BS1, BS2)
PAGEL
XTAL1
DATA
BS1
XA0
XA1
1. The timing requirements shown in
ing operation.
Data & Contol
RDY/BSY
PAGEL
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
WR
t
t
BVPH
DVXH
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
Figure 133
t
t
t
t
t
XLXH
XLDX
PLBX
XLWL
PLWL
(i.e., t
t
(HIGH BYTE)
BVWL
LOAD DATA
DATA (High Byte)
DVXH
t
t
WL WH
XLPH
, t
WLRL
LOAD DATA
XHXL
, and t
t
ATmega16(L)
PLXH
t
WLBX
XLDX
LOAD ADDRESS
(LOW BYTE)
) also apply to load-
ADDR1 (Low Byte)
t
WLRH
(1)
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