DSPIC33FJ64GS606-I/MR Microchip Technology, DSPIC33FJ64GS606-I/MR Datasheet - Page 200

• Manufacturer Part Number: DSPIC33FJ64GS606-I/MR
• Description: IC MCU/DSP 64KB FLASH 64QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS606-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Ram Size: 9K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 58
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
10.2.2
The following occur in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC also
The device will wake-up from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAV instruction, or the first instruction in the ISR.
10.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
10.3
The
consumption are changing clock speed and invoking
one
circumstances, this may not be practical. For example,
it may be necessary for an application to maintain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving
completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70591C-page 200
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.5
“Peripheral Module Disable”).
remains active.
of
preferred
Doze Mode
the
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
mode
power-saving
strategies
can
stop
for
modes.
reducing
communications
In
power
some
Preliminary
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>).
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is placed in Doze mode with a clock frequency
ratio of 1:4, the CAN module continues to communicate
at the required bit rate of 500 kbps, but the CPU now
starts executing instructions at a frequency of 5 MIPS.
10.4
Typically, many applications need either a high
resolution duty cycle or phase offset (for fixed
frequency operation) or a high resolution PWM period
for variable frequency modes of operation (such as
Resonant mode). Very few applications require both
high resolution modes simultaneously.
The HRPDIS and the HRDDIS bits in the AUXCONx
registers permit the user to disable the circuitry associ-
ated with the high resolution duty cycle and PWM
period to reduce the operating current of the device.
If the HRDDIS bit is set, the circuitry associated with
the high resolution duty cycle, phase offset, and dead
time for the respective PWM generator is disabled. If
the HRPDIS bit is set, the circuitry associated with the
high resolution PWM period for the respective PWM
generator is disabled.
When the HRPDIS bit is set, the smallest unit of
measure for the PWM period is 8.32 ns.
If the HRDDIS bit is set, the smallest unit of measure
for the PWM duty cycle, phase offset and dead time is
8.32 ns.
PWM Power-Saving Features
There
 2010 Microchip Technology Inc.
are
eight
possible