DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 6

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

dsPIC30F3014/4013
5. Module: DISI Instruction
6. Module: Early Termination of Nested DO
DS80397A-page 6
When a user executes a DISI #7, for example,
this will disable interrupts from 7 + 1 cycles (7 + the
DISI instruction itself). In this case, the DISI
instruction uses a counter which counts down from
7 to 0. The counter is loaded with 7 at the end of
the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded, but
the DISI state machine does not properly
re-engage and continue to disable interrupts. At
this point, all interrupts are enabled. The next time
the user code executes a DISI instruction, the
feature will act normally and block interrupts.
In summary, it is only when DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error. In this case, the DISI counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT (CORCON<11>) bit will produce unexpected
results. Specifically, the device may continue
executing code within the outer DO loop forever.
This erratum does not affect the operation of the
MPLAB C30 compiler.
Work around
The application should save the DCOUNT SFR
prior to entering the inner DO loop and restore it
upon exiting the inner DO loop. This work around is
shown in Example 7.
Loops
EXAMPLE 7:
7. Module: 32 kHz Low-Power (LP)
8. Module: Data Converter Interface (DCI)
LOOP1: MOV
LOOP0:
Note:
The LP oscillator is located on the SOSCO and
SOSCI device pins and serves as a secondary
crystal clock source for low-power operation. The
LP oscillator can also drive Timer1 for a real-time
clock application. The LP oscillator does not
function when the device is placed in Sleep mode.
Work around
If the application needs to wake-up periodically
from Sleep mode using an internal timer, the
Watchdog Timer may be enabled prior to entering
Sleep mode. When the Watchdog Timer expires,
code execution will resume from the instruction
immediately following the SLEEP instruction.
The DCI module is enabled by setting the DCIEN
(DCICON1<15>) bit and disabled by clearing the
DCIEN bit. Once enabled, if the DCI module is
subsequently disabled by the application, the
module does not release the ownership of the
COFS, CSCK, CSDI and CSDO pins to the
associated port functions (RB9, RB10, RB11 and
RB12).
Work around
After disabling the DCI module by clearing the
DCIEN bit, the application should further set the
DCI Module Disable bit, DCIMD (PMD1<8>). The
port functions associated with the DCI module
(RB9, RB10, RB11 and RB12) may now be used.
.include “p30fxxxx.inc”
.......
DO #CNT1, LOOP0
....
PUSH DCOUNT
DO
....
BTSS Flag, #0
BSET CORCON, #EDT
....
....
POP
...
For details on the functionality of
EDT bit, see section 2.9.2.4
in the dsPIC30F Family Reference
Manual.
MOV W5, W8
Oscillator
#CNT2, LOOP1
W1, W5
DCOUNT
SAVE AND RESTORE
DCOUNT
© 2008 Microchip Technology Inc.
;Outer loop start
;Save DCOUNT
;Inner loop
;starts
;Terminate inner
;DO-loop early
;Inner loop ends
;Restore DCOUNT
;Outer loop ends