PIC16LF876-04I/SO Microchip Technology, PIC16LF876-04I/SO Datasheet - Page 110

• Manufacturer Part Number: PIC16LF876-04I/SO
• Description: IC MCU FLASH 8KX14 EE A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF876-04I/SO

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 22
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP, PSP, USART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 4 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F87X
FIGURE 10-11:
10.4
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
10.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
DS30292C-page 108
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
19h
8Ch
98h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
Address
RC7/RX/DT pin
RC6/TX/CK pin
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
Write to
bit SREN
SREN bit
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
USART Synchronous Slave Mode
USART SYNCHRONOUS SLAVE
TRANSMIT
INTCON
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
Name
Q2
’0’
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’.
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
USART Transmit Register
Baud Rate Generator Register
PSPIE
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
PSPIF
SPEN
CSRC
Bit 7
GIE
(1)
(1)
bit0
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
SREN
TXEN
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RCIF
RCIE
bit1
Bit 5
T0IE
CREN ADDEN
SYNC
INTE
TXIF
TXIE
Bit 4
bit2
SSPIF
SSPIE
RBIE
Bit 3
—
bit3
e)
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
CCP1IF TMR2IF TMR1IF 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
BRGH
FERR
Bit 2
T0IF
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
bit4
OERR
TRMT
INTF
Bit 1
bit5
RX9D
TX9D
Bit 0
R0IF
bit6
2001 Microchip Technology Inc.
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
POR, BOR
Value on:
bit7
Q1 Q2 Q3 Q4
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
Value on all
0000 000u
RESETS
other
’0’