DSPIC33FJ128GP708-I/PT

Manufacturer Part NumberDSPIC33FJ128GP708-I/PT
DescriptionIC DSPIC MCU/DSP 128K 80TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128GP708-I/PT datasheets
 


Specifications of DSPIC33FJ128GP708-I/PT

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case80-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed40 MIPs
ConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o69Ram Size16K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 24x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
ProductDSCsData Bus Width16 bit
Processor SeriesDSPIC33FCoredsPIC
Maximum Clock Frequency40 MHzNumber Of Programmable I/os69
Data Ram Size16 KBMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033Minimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size-  
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dsPIC33FJXXXGPX06/X08/X10
Data Sheet
High-Performance,
16-Bit Digital Signal Controllers
© 2009 Microchip Technology Inc.
DS70286C

DSPIC33FJ128GP708-I/PT Summary of contents

  • Page 1

    ... Microchip Technology Inc. High-Performance, 16-Bit Digital Signal Controllers Data Sheet DS70286C ...

  • Page 2

    ... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 3

    ... available interrupt sources • five external interrupts • Seven programmable priority levels • Five processor exceptions © 2009 Microchip Technology Inc. dsPIC33FJXXXGPX06/X08/X10 Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-Change pins • Output pins can drive from 3.0V to 3.6V • ...

  • Page 4

    ... Industrial temperature • Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 80-pin TQFP (12x12x1 mm) • 64-pin TQFP (10x10x1 mm) Note: See the device variant tables for exact peripheral features per device. © 2009 Microchip Technology Inc. ...

  • Page 5

    ... Note 1: RAM size is inclusive of 2 Kbytes DMA RAM. 2: Maximum I/O pin count includes pins shared by the peripheral functions. ...

  • Page 6

    ... SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF DS70286C-page dsPIC33FJ64GP206 41 40 dsPIC33FJ128GP206 Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2009 Microchip Technology Inc. ...

  • Page 7

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF © 2009 Microchip Technology Inc dsPIC33FJ64GP306 41 dsPIC33FJ128GP306 Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 ...

  • Page 8

    ... SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF DS70286C-page dsPIC33FJ256GP506 Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2009 Microchip Technology Inc. ...

  • Page 9

    ... AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGEC3/AN1/V -/CN3/RB1 15 REF PGED3/AN0/V +/CN2/RB0 16 REF © 2009 Microchip Technology Inc dsPIC33FJ64GP706 41 dsPIC33FJ128GP706 Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 ...

  • Page 10

    ... SS2/CN11/RG9 TMS/AN20/INT1/RA12 13 TDO/AN21/INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGEC3/AN1/CN3/RB1 19 PGED3/AN0/CN2/RB0 20 DS70286C-page dsPIC33FJ64GP708 51 dsPIC33FJ128GP708 Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 SDA2/INT4/RA3 SCL2/INT3/RA2 V SS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 V DD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2009 Microchip Technology Inc. ...

  • Page 11

    ... AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 20 AN5/CN7/RB5 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 © 2009 Microchip Technology Inc. dsPIC33FJ64GP310 dsPIC33FJ128GP310 = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 71 IC4/RD11 IC3/RD10 70 69 IC2/RD9 68 IC1/RD8 INT4/RA15 67 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 ...

  • Page 12

    ... AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 25 PGED3/AN0/CN2/RB0 DS70286C-page 10 dsPIC33FJ256GP510 = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 71 IC3/RD10 70 IC2/RD9 69 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 60 TDI/RA4 SDA2/RA3 59 58 SCL2/RA2 57 SCL1/RG2 SDA1/RG3 56 SCK1/INT0/RF6 55 54 SDI1/RF7 53 SDO1/RF8 U1RX/RF2 52 51 U1TX/RF3 © 2009 Microchip Technology Inc. ...

  • Page 13

    ... AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGEC3/AN1/CN3/RB1 24 PGED3/AN0/CN2/RB0 25 © 2009 Microchip Technology Inc. dsPIC33FJ64GP710 dsPIC33FJ128GP710 dsPIC33FJ256GP710 = Pins are tolerant PGEC2/SOSCO/T1CK/CN0/RC14 73 PGED2/SOSCI/CN1/RC13 OC1/RD0 72 71 IC4/RD11 70 IC3/RD10 IC2/RD9 69 68 IC1/RD8 INT4/RA15 67 66 INT3/RA14 OSC2/CLKO/RC15 63 OSC1/CLKIN/RC12 TDO/RA5 ...

  • Page 14

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70286C-page 12 © 2009 Microchip Technology Inc. ...

  • Page 15

    ... The dsPIC33FJXXXGPX06/X08/X10 General Purpose Family of device includes devices with a wide range of pin counts (64, 80 and 100), different program memory ...

  • Page 16

    ... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ DCI ADC1,2 PWM1-8 CN1-23 SPI1,2 I2C1,2 PORTA DMA RAM PORTB DMA 16 Controller PORTC PORTD 16 PORTE 16 PORTF 16 PORTG 16 ECAN1,2 UART1,2 © 2009 Microchip Technology Inc. ...

  • Page 17

    ... RF12-RF13 I/O ST Legend: CMOS = CMOS compatible input or output Schmitt Trigger input with CMOS levels; © 2009 Microchip Technology Inc. Description Analog input channels. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. External clock source input. Always associated with OSC1 pin function. ...

  • Page 18

    ... Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input Output Power I = Input © 2009 Microchip Technology Inc. ...

  • Page 19

    ... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2009 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...

  • Page 20

    ... Overstress (EOS). Ensure that the MCLR pin V IH for and V ) and fast signal shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F recommended. A suggested and V specifications are met 470 will limit any current flowing into and V specifications are met. IL © 2009 Microchip Technology Inc. ...

  • Page 21

    ... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “ ...

  • Page 22

    ... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. DS70286C-page © 2009 Microchip Technology Inc. ...

  • Page 23

    ... X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and © 2009 Microchip Technology Inc. Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific ...

  • Page 24

    ... Data Latch PCH PCL X RAM Y RAM Address Address Loop Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2009 Microchip Technology Inc. ...

  • Page 25

    ... Registers AD39 DSP AccA Accumulators AccB PC22 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2009 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...

  • Page 26

    ... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70286C-page 24 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...

  • Page 27

    ... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2009 Microchip Technology Inc. (2) DS70286C-page 25 ...

  • Page 28

    ... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70286C-page 26 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...

  • Page 29

    ... W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2009 Microchip Technology Inc. 3.6 DSP Engine The DSP ...

  • Page 30

    ... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70286C-page 28 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2009 Microchip Technology Inc. ...

  • Page 31

    ... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2009 Microchip Technology Inc. 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true, or complement data into the other input ...

  • Page 32

    ... Section 3.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. subject to data saturation (see © 2009 Microchip Technology Inc. ...

  • Page 33

    ... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2009 Microchip Technology Inc. 3.6.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

  • Page 34

    ... NOTES: DS70286C-page 32 © 2009 Microchip Technology Inc. ...

  • Page 35

    ... Reserved Device Configuration Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2009 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33FJXXXGPX06/X08/X10 instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4 ...

  • Page 36

    ... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word Instruction Width PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2009 Microchip Technology Inc. ...

  • Page 37

    ... Data byte writes only write to the corresponding side of the array or register which matches the byte address. © 2009 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...

  • Page 38

    ... Mapped into Program Memory 0xFFFF DS70286C-page 36 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2009 Microchip Technology Inc. ...

  • Page 39

    ... Kbyte 0x2801 SRAM Space 0x3FFF 0x4001 0x47FF 0x4801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2009 Microchip Technology Inc. LSB Address 16 bits MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE ...

  • Page 40

    ... Optionally Mapped into Program Memory 0xFFFF DS70286C-page 38 LSB Address 16 bits MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x47FE 0x4800 Y Data RAM (Y) 0x77FE 0x7800 DMA RAM 0x7FFE 0x8000 X Data Unimplemented (X) 0xFFFE © 2009 Microchip Technology Inc. 8 Kbyte Near Data Space ...

  • Page 41

    ... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2009 Microchip Technology Inc. 4.2.6 DMA RAM Every dsPIC33FJXXXGPX06/X08/X10 device contains 2 Kbytes of dual ported DMA RAM located at the end of Y data space ...

  • Page 42

    TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

  • Page 43

    TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XBREV 0050 BREN DISICNT 0052 — — BSRAM 0750 — — — SSRAM 0752 — — — Legend unknown value on ...

  • Page 44

    TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXGPX10 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE ...

  • Page 45

    TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 ...

  • Page 46

    TABLE 4-6: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

  • Page 47

    TABLE 4-7: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...

  • Page 48

    TABLE 4-8: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...

  • Page 49

    TABLE 4-9: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — I2C1TRN 0202 — — — I2C1BRG 0204 — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL I2C1STAT 0208 ...

  • Page 50

    TABLE 4-11: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...

  • Page 51

    TABLE 4-15: ADC1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...

  • Page 52

    TABLE 4-17: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...

  • Page 53

    TABLE 4-17: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB 03CE DMA6PAD ...

  • Page 54

    TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = FOR dsPIC33FJXXXGP506/510/706/708/710 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — ...

  • Page 55

    TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR dsPIC33FJXXXGP506/510/706/708/710 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...

  • Page 56

    TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR dsPIC33FJXXXGP506/510/706/708/710 DEVICES ONLY (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C SID<10:3> C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> ...

  • Page 57

    TABLE 4-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 C2CTRL1 0500 — — CSIDL C2CTRL2 0502 — — — C2VEC 0504 — — — C2FCTRL ...

  • Page 58

    TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0500 - 051E C2BUFPNT1 0520 F3BP<3:0> C2BUFPNT2 0522 F7BP<3:0> C2BUFPNT3 0524 F11BP<3:0> C2BUFPNT4 0526 F15BP<3:0> C2RXM0SID ...

  • Page 59

    TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C2RXF10EID 056A EID<15:8> C2RXF11SID 056C SID<10:3> C2RXF11EID 056E EID<15:8> C2RXF12SID 0570 SID<10:3> C2RXF12EID 0572 EID<15:8> ...

  • Page 60

    TABLE 4-24: DCI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name DCICON1 0280 DCIEN — DCISIDL — DCICON2 0282 — — — — DCICON3 0284 — — — — DCISTAT 0286 — — — — ...

  • Page 61

    TABLE 4-27: PORTC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 PORTC 02CE RC15 RC14 RC13 RC12 LATC 02D0 LATC15 LATC14 LATC13 LATC12 Legend unknown value ...

  • Page 62

    TABLE 4-31: PORTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 PORTG 02E6 RG15 RG14 RG13 RG12 LATG 02E8 LATG15 LATG14 LATG13 LATG12 ODCG 06E4 ODCG15 ODCG14 ODCG13 ...

  • Page 63

    ... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. 4.2.8 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM protection features which enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...

  • Page 64

    ... Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing © 2009 Microchip Technology Inc. ...

  • Page 65

    ... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2009 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...

  • Page 66

    ... BREN (XBREV<15>) bit, then a write to using the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled disabled. However, Modulo © 2009 Microchip Technology Inc. ...

  • Page 67

    ... TABLE 4-36: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2009 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal ...

  • Page 68

    ... PC<22:1> 0 0xx xxxx xxxx xxxx TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx © 2009 Microchip Technology Inc. <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...

  • Page 69

    ... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. Program Counter 0 23 bits ...

  • Page 70

    ... TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area © 2009 Microchip Technology Inc. ...

  • Page 71

    ... PAG is mapped into the upper half of the data memory space... © 2009 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...

  • Page 72

    ... NOTES: DS70286C-page 70 © 2009 Microchip Technology Inc. ...

  • Page 73

    ... Using 1/0 Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions ...

  • Page 74

    ... AAh to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. stalls (waits) until the PROGRAMMING TIME T FRC Accuracy % FRC Tuning % 11064 Cycles = 1 + 0.02 1 0.00375 – 11064 Cycles = 1 0.02 – 1 0.00375 – © 2009 Microchip Technology Inc. ...

  • Page 75

    ... Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...

  • Page 76

    ... NVMKEY<7:0>: Key Register (Write Only) bits DS70286C-page 74 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...

  • Page 77

    ... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...

  • Page 78

    ... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2009 Microchip Technology Inc. ...

  • Page 79

    ... DD Trap Conflict Illegal Opcode Uninitialized W Register © 2009 Microchip Technology Inc. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...

  • Page 80

    ... SWDTEN bit setting. DS70286C-page 78 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 — — VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 81

    ... Clock Source Determinant POR Oscillator Configuration bits (FNOSC<2:0>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR © 2009 Microchip Technology Inc. Setting Event Trap conflict event Illegal opcode or uninitialized W register access MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction ...

  • Page 82

    ... Reset and the programmed values of the oscillator Configuration bits in the FOSC Configuration register. FSCM Notes Delay — FSCM FSCM LOCK FSCM — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — auto- FSCM © 2009 Microchip Technology Inc. ...

  • Page 83

    ... These are summarized in Table 7-1 and Table 7-2. © 2009 Microchip Technology Inc. 7.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the ...

  • Page 84

    ... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70286C-page 82 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2009 Microchip Technology Inc. ...

  • Page 85

    ... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C DMA0 – DMA Channel 0 0x00011E IC2 – ...

  • Page 86

    ... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Trap Reserved Reserved © 2009 Microchip Technology Inc. ...

  • Page 87

    ... The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2009 Microchip Technology Inc. The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...

  • Page 88

    ... EDT R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...

  • Page 89

    ... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...

  • Page 90

    ... STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70286C-page 88 © 2009 Microchip Technology Inc. ...

  • Page 91

    ... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

  • Page 92

    ... Interrupt request has not occurred DS70286C-page 90 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA01IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 93

    ... Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. DS70286C-page 91 ...

  • Page 94

    ... Interrupt request has not occurred DS70286C-page 92 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IF DMA21IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 95

    ... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. DS70286C-page 93 ...

  • Page 96

    ... Interrupt request has not occurred DS70286C-page 94 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF R/W-0 R/W-0 R/W-0 DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 97

    ... Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. DS70286C-page 95 ...

  • Page 98

    ... Interrupt request has not occurred DS70286C-page 96 R/W-0 R/W-0 U-0 DCIIF DCIEIF — R/W-0 R/W-0 R/W-0 T9IF T8IF MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — C2IF bit 8 R/W-0 R/W-0 SI2C2IF T7IF bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 99

    ... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

  • Page 100

    ... Interrupt request not enabled DS70286C-page 98 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 R/W-0 R/W-0 DMA0IE T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 101

    ... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. DS70286C-page 99 ...

  • Page 102

    ... Interrupt request not enabled DS70286C-page 100 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IE DMA2IE bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 103

    ... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. DS70286C-page 101 ...

  • Page 104

    ... Interrupt request not enabled DS70286C-page 102 R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE R/W-0 R/W-0 R/W-0 DMA3IE C1IE C1RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IE IC6IE bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 105

    ... Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. DS70286C-page 103 ...

  • Page 106

    ... Interrupt request not enabled DS70286C-page 104 R/W-0 R/W-0 U-0 DCIIE DCIEIE — R/W-0 R/W-0 R/W-0 T9IE T8IE MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — C2IE bit 8 R/W-0 R/W-0 SI2C2IE T7IE bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 107

    ... U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 ...

  • Page 108

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 106 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 109

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 110

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 108 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 111

    ... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

  • Page 112

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 110 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 113

    ... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 114

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 112 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 115

    ... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 116

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 117

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 118

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC6IP<2:0> bit 8 R/W-0 R/W-0 IC6IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 119

    ... Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...

  • Page 120

    ... Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 118 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 R/W-0 T7IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 121

    ... Unimplemented: Read as ‘0’ bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...

  • Page 122

    ... Interrupt source is disabled DS70286C-page 120 R/W-0 U-0 U-0 — — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 C2IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 123

    ... Unimplemented: Read as ‘0’ bit 2-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...

  • Page 124

    ... Unimplemented: Read as ‘0’ DS70286C-page 122 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2EIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 125

    ... Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

  • Page 126

    ... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70286C-page 124 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

  • Page 127

    ... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...

  • Page 128

    ... NOTES: DS70286C-page 126 © 2009 Microchip Technology Inc. ...

  • Page 129

    ... DCI ECAN1 Reception ECAN1 Transmission ECAN2 Reception ECAN2 Transmission © 2009 Microchip Technology Inc. The DMA controller features eight identical data transfer channels. Each channel has its own set of control and status registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs, or from peripheral SFRs to buffers in DMA RAM ...

  • Page 130

    ... An additional pair of status registers, DMACS0 and DMACS1, are common to all DMAC channels. DS70286C-page 128 Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2009 Microchip Technology Inc. ...

  • Page 131

    ... MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 U-0 HALF NULLW — ...

  • Page 132

    ... U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) (2) (2) IRQSEL4 IRQSEL3 IRQSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) U-0 U-0 — — — bit 8 R/W-0 R/W-0 (2) (2) (2) IRQSEL1 IRQSEL0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 133

    ... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as ‘0’ ...

  • Page 134

    ... U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (2) CNT<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 (2) CNT<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 135

    ... XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2009 Microchip Technology Inc. R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 ...

  • Page 136

    ... Write collision detected write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected DS70286C-page 134 © 2009 Microchip Technology Inc. ...

  • Page 137

    ... PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected © 2009 Microchip Technology Inc. U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 ...

  • Page 138

    ... DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70286C-page 136 R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

  • Page 139

    ... SOSCI Note 1: See Figure 9-2 for PLL details the Oscillator is used with modes, an extended parallel resistor with the value must be connected. © 2009 Microchip Technology Inc. • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • The internal FRC oscillator can also be used with ...

  • Page 140

    ... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by: OSC EQUATION 9-2: F OSC OSC © 2009 Microchip Technology Inc. Configuration bits, is divided OSC ) and the defines the the F ...

  • Page 141

    ... Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2009 Microchip Technology Inc. EQUATION 9-3: F ------------- 0.8-8.0 MHz 100-200 MHz ...

  • Page 142

    ... PLL modes. DS70286C-page 140 (1) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) © 2009 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...

  • Page 143

    ... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. (1) (CONTINUED) ...

  • Page 144

    ... Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70286C-page 142 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 145

    ... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...

  • Page 146

    ... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. DS70286C-page 144 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 147

    ... NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2009 Microchip Technology Inc valid clock switch has been initiated, the LOCK (OSCCON<3>) status bits are cleared. ...

  • Page 148

    ... NOTES: DS70286C-page 146 © 2009 Microchip Technology Inc. ...

  • Page 149

    ... EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes dsPIC33FJXXXGPX06/X08/X10 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...

  • Page 150

    ... If a PMD bit is set, the corresponding module is disabled after a delay of 1 instruction cycle. Similarly PMD bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). consumption in event-driven ® DSC © 2009 Microchip Technology Inc. ...

  • Page 151

    ... SPI2 module is enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 C2MD: ECAN2 Module Disable bit 1 = ECAN2 module is disabled 0 = ECAN2 module is enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — R/W-0 R/W-0 R/W-0 ...

  • Page 152

    ... REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 1 C1MD: ECAN2 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled DS70286C-page 150 © 2009 Microchip Technology Inc. ...

  • Page 153

    ... OC6MD: Output Compare 6 Module Disable bit 1 = Output Compare 6 module is disabled 0 = Output Compare 6 module is enabled bit 4 OC5MD: Output Compare 5 Module Disable bit 1 = Output Compare 5 module is disabled 0 = Output Compare 5 module is enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 IC5MD IC4MD IC3MD R/W-0 ...

  • Page 154

    ... Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70286C-page 152 © 2009 Microchip Technology Inc. ...

  • Page 155

    ... Unimplemented: Read as ‘0’ bit 1 I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 AD2MD: AD2 Module Disable bit 1 = AD2 module is disabled 0 = AD2 module is enabled © 2009 Microchip Technology Inc. R/W-0 U-0 U-0 T6MD — — U-0 U-0 U-0 — ...

  • Page 156

    ... NOTES: DS70286C-page 154 © 2009 Microchip Technology Inc. ...

  • Page 157

    ... CK Data Latch Read LAT Read Port © 2009 Microchip Technology Inc. When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port ...

  • Page 158

    ... CN pins. Setting in either any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. capable of detecting input © 2009 Microchip Technology Inc. ...

  • Page 159

    ... SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal Figure 12-1 presents a block diagram of the 16-bit timer module ...

  • Page 160

    ... Unimplemented: Read as ‘0’ DS70286C-page 158 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 161

    ... For 32-bit timer/counter operation, Timer2, Timer4, Timer6 or Timer8 is the least significant word; Timer3, Timer5, Timer7 or Timer9 is the most significant word of the 32-bit timers. © 2009 Microchip Technology Inc. Note: For 32-bit operation, T3CON, T5CON, T7CON and T9CON control bits are ignored. Only T2CON, T4CON, T6CON and T8CON control bits are used for setup and control ...

  • Page 162

    ... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70286C-page 160 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...

  • Page 163

    ... FIGURE 13-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2009 Microchip Technology Inc. dsPIC33FJXXXGPX06/X08/X10 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TCS TGATE DS70286C-page 161 ...

  • Page 164

    ... Note 1: The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins. DS70286C-page 162 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (1) — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 165

    ... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: The TyCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins. © 2009 Microchip Technology Inc. U-0 U-0 (2) — ...

  • Page 166

    ... NOTES: DS70286C-page 164 © 2009 Microchip Technology Inc. ...

  • Page 167

    ... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. 2. Capture timer value on every edge (rising and falling) 3. Prescaler Capture Event modes -Capture timer value on every 4th rising edge ...

  • Page 168

    ... Note 1: Timer selections may vary. Refer to the device data sheet for details. DS70286C-page 166 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 169

    ... An ‘x’ signal, register or bit name denotes the number of the output compare channels. 2: The OCFA pin controls OC1 through OC4. The OCFB pin controls OC5 through OC8. © 2009 Microchip Technology Inc. The state of the output pin changes when the timer value matches the Compare register value ...

  • Page 170

    ... OCx rising and falling edge OCx falling edge 0 OCx falling edge 0 ‘0’, if OCxR is zero No interrupt ‘1’, if OCxR is non-zero ‘0’, if OCxR is zero OCFA falling edge for OC1 to OC4 ‘1’, if OCxR is non-zero Timer is Reset on Period Match © 2009 Microchip Technology Inc. — ...

  • Page 171

    ... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

  • Page 172

    ... NOTES: DS70286C-page 170 © 2009 Microchip Technology Inc. ...

  • Page 173

    ... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. Each SPI module consists of a 16-bit shift register, SPIxSR (where 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates various status conditions. ...

  • Page 174

    ... Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70286C-page 172 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...

  • Page 175

    ... Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ...

  • Page 176

    ... Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70286C-page 174 (2) (2) © 2009 Microchip Technology Inc. ...

  • Page 177

    ... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

  • Page 178

    ... NOTES: DS70286C-page 176 © 2009 Microchip Technology Inc. ...

  • Page 179

    ... I C master operation with 7 or 10-bit address For details about the communication sequence in each of these modes, please refer to the “dsPIC33F Family Reference Manual”. © 2009 Microchip Technology Inc Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable ...

  • Page 180

    ... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...

  • Page 181

    ... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...

  • Page 182

    ... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70286C-page 180 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master master) © 2009 Microchip Technology Inc. ...

  • Page 183

    ... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. U-0 U-0 R/C-0 HS — — ...

  • Page 184

    ... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70286C-page 182 2 C slave device address byte. © 2009 Microchip Technology Inc. ...

  • Page 185

    ... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

  • Page 186

    ... NOTES: DS70286C-page 184 © 2009 Microchip Technology Inc. ...

  • Page 187

    ... UART1 or UART2 transmission or reception DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> = 00). © 2009 Microchip Technology Inc. • Hardware Flow Control Option with UxCTS and UxRTS pins • Fully Integrated Baud Rate Generator with 16-bit Prescaler • ...

  • Page 188

    ... DS70286C-page 186 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 189

    ... Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. MODE REGISTER (CONTINUED) x DS70286C-page 187 ...

  • Page 190

    ... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...

  • Page 191

    ... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED transition) will reset ...

  • Page 192

    ... NOTES: DS70286C-page 190 © 2009 Microchip Technology Inc. ...

  • Page 193

    ... Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Programmable clock source © 2009 Microchip Technology Inc. • Programmable link to input capture module (IC2 for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode The CAN bus module consists of a protocol engine and message buffering/control ...

  • Page 194

    ... RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter RXF7 Filter RXF6 Filter RXF5 Filter RXF4 Filter RXF3 Filter RXF2 Filter RXF1 Filter RXF0 Filter Buffer RXM2 Mask RXM1 Mask RXM0 Mask Control CPU Configuration Bus Logic Interrupts © 2009 Microchip Technology Inc. ...

  • Page 195

    ... The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. © 2009 Microchip Technology Inc. Note: Typically, if the CAN module is allowed to transmit in a particular mode of operation ...

  • Page 196

    ... Use buffer window DS70286C-page 194 R/W-0 r-0 R/W-1 ABAT — U-0 R/W-0 U-0 — CANCAP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 REQOP<2:0> bit 8 U-0 R/W-0 — WIN bit Bit is Reserved © 2009 Microchip Technology Inc. ...

  • Page 197

    ... DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R-0 ...

  • Page 198

    ... TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70286C-page 196 R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 R-0 ICODE<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

  • Page 199

    ... Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = RB31 buffer 11110 = RB30 buffer • • • 00001 = TRB1 buffer 00000 = TRB0 buffer © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 FSA< ...

  • Page 200

    ... TRB1 buffer 000000 = TRB0 buffer DS70286C-page 198 R-0 R-0 R-0 FBP<5:0> R-0 R-0 R-0 FNRB<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...