ATMEGA645V-8AU Atmel, ATMEGA645V-8AU Datasheet - Page 81

• Manufacturer Part Number: ATMEGA645V-8AU
• Description: IC AVR MCU FLASH 64K 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 54
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 8MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Data Rom Size: 2 KB
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4
13.4.1
13.4.2
13.4.3
13.4.4
2570M–AVR–04/11
Register Description
MCUCR – MCU Control Register
PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins Address
Table 13-21. Overriding Signals for Alternate Functions in PH3:0
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 61
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x02 (0x22)
Read/Write
Initial Value
Bit
0x01 (0x21)
Read/Write
Initial Value
Bit
0x00 (0x20)
Read/Write
Initial Value
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
PORTA7
PINA7
DDA7
R/W
R/W
R/W
JTD
R/W
N/A
7
0
7
0
7
7
0
PJ3/PCINT27
0
0
0
0
0
0
–
PCINT27 •
PCIE0
0
–
–
PORTA6
PINA6
DDA6
R/W
R/W
R/W
N/A
6
0
6
0
6
R
6
–
0
for more details about this feature.
PORTA5
PINA5
DDA5
R/W
R/W
R/W
N/A
5
0
5
0
5
R
5
–
0
PJ2/PCINT26
0
0
0
0
0
0
–
PCINT26 •
PCIE0
0
–
–
PORTA4
PINA4
DDA4
R/W
R/W
R/W
N/A
4
0
4
0
4
PUD
R/W
4
0
ATmega325/3250/645/6450
PORTA3
PINA3
DDA3
R/W
R/W
R/W
N/A
3
0
3
0
3
R
3
–
0
PJ1/PCINT25
0
0
0
0
0
0
–
PCINT25 •
PCIE0
0
–
–
PORTA2
PINA2
DDA2
R/W
R/W
R/W
N/A
2
0
2
0
2
R
2
–
0
PORTA1
PINA1
DDA1
R/W
R/W
R/W
N/A
IVSEL
1
0
1
0
1
R/W
1
0
PJ0/PCINT24
0
0
0
0
0
0
–
PCINT24 •
PCIE0
0
–
–
PORTA0
PINA0
DDA0
R/W
R/W
R/W
N/A
IVCE
R/W
0
0
0
0
0
0
0
PORTA
MCUCR
DDRA
PINA
“Con-
81