PIC18LF4539-I/PT Microchip Technology, PIC18LF4539-I/PT Datasheet - Page 238

• Manufacturer Part Number: PIC18LF4539-I/PT
• Description: IC MCU FLASH 12KX16 EE AD 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4539-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18FXX39
MOVFF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
DS30485A-page 236
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
REG1
REG2
REG1
REG2
Q1
No dummy
register 'f'
operation
Move f to f
[ label ]
0 ≤ f
0 ≤ f
(f
None
The contents of source register 'f
are moved to destination register
'f
anywhere in the 4096 byte data
space (000h to FFFh), and location
of destination 'f
where from 000h to FFFh.
Either source or destination can be
W (a useful special situation).
MOVFF is particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
The MOVFF instruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
Note:
2
2 (3)
MOVFF
d
Read
s
(src)
read
'. Location of source 'f
) → f
1100
1111
No
Q2
=
=
=
=
s
d
≤ 4095
≤ 4095
d
0x33
0x11
0x33,
0x33
The MOVFF instruction
should not be used to mod-
ify interrupt settings while
any interrupt is enabled.
See Section 8.0 for more
information.
REG1, REG2
MOVFF f
ffff
ffff
operation
Process
Data
No
Q3
d
' can also be any-
ffff
ffff
s
,f
d
register 'f'
s
operation
' can be
(dest)
Write
No
Q4
fff
fff
Preliminary
f
f
s
s
d
'
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
BSR register
BSR register
Q1
Read literal
Move literal to low nibble in BSR
[ label ]
0 ≤ k ≤ 255
k → BSR
None
The 8-bit literal 'k' is loaded into
the Bank Select Register (BSR).
1
1
MOVLB
0000
Q2
'k'
=
=
 2002 Microchip Technology Inc.
0x02
0x05
5
MOVLB k
0001
Process
Data
Q3
kkkk
literal 'k' to
Write
BSR
Q4
kkkk