DSPIC30F6012A-30I/PT Microchip Technology, DSPIC30F6012A-30I/PT Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F6012A-30I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012A30IP

dsPIC30F6011A/6012A/6013A/6014A
TABLE 2:
DS80457B-page 2
Operations
Note 1:
OSC2 Pin
Compare
Compare
Module
Output
Output
Sleep
Mode
Timer
I
CPU
CAN
CPU
CPU
PSV
2
PLL
I
I
I
I
I/O
C™
2
2
2
2
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Modifications
Bus Collision
RX Filters 3,
Slave Mode
Sleep Mode
PWM Mode
Lock Status
Multiplexed
Addressing
Addressing
Addressing
Instructions
Instruction
Instruction
MAC Class
Digital I/O
RC15 as
Feature
Port Pin
with IC1
Address
SILICON ISSUE SUMMARY
4 and 5
with ±4
DAW.b
10-bit
10-bit
10-bit
DISI
bit
—
—
—
Number
Item
12.
10.
11.
13.
14.
15.
16.
17.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The Decimal Adjust instruction, DAW.b, may improperly clear the
Carry bit, C (SR<0>).
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after the
glitch.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also increase
beyond the specifications listed in the device data sheet.
The I
I
The Port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an oscillator failure trap even when the
PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes when
accessing the first four bytes of any PSV page.
The 10-bit slave does not set the RBF flag or load the I2CxRCV
register, on address match if the Least Significant bits (LSbs) of
the address are the same as the 7-bit reserved addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a bus
collision in a multi-master configuration.
CAN Receive filters 3, 4 and 5 may not work for a given
combination of instruction cycle speed and CAN bit time quanta.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification will cause an address error
trap.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
The output compare module will produce a glitch on the output
when an I/O pin is initially set high and the module is configured
to drive the pin low at a specified time.
For this revision of silicon, pin OSC2/RC15 is operational for
digital I/O and CLKOUT only in specific oscillator modes.
2
C slave.
2
C module loses incoming data bytes when operating as an
2
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
C module is enabled, the dsPIC
Issue Summary
®
DSC device
2
C devices, the
© 2010 Microchip Technology Inc.
Revisions
A2 B0 B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)