AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 17

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

6. Memories
6.1
6.2
32054FS–AVR32–09/09
Embedded Memories
Physical Memory Map
•
The system bus is implemented as an HSB bus matrix. All system bus addresses are fixed, and
they are never remapped in any way, not even in boot. Note that AT32AP7002 by default uses
segment translation, as described in the AVR32 Architecture Manual. The 32 bit physical
address space is mapped as follows:
Table 6-1.
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, MCFG2 is associated
with the HSB-HSB bridge.
Start Address
0x0000_0000
0x0400_0000
0x0800_0000
0x0C00_0000
0x1000_0000
0x2000_0000
0x2400_0000
0x2400_4000
0xFF00_0000
0xFF20_0000
0xFF30_0000
0xFFE0_0000
0xFFF0_0000
32 Kbyte SRAM
– Implemented as two 16Kbyte blocks
– Single cycle access at full bus speed
AT32AP7002 Physical Memory Map
Size
16 Kbyte
16 Kbyte
4 Kbyte
1 KByte
1 MByte
1 MByte
1 MByte
64 Mbyte
64 Mbyte
64 Mbyte
64 Mbyte
256 Mbyte
64 Mbyte
Device
EBI SRAM CS0
EBI SRAM CS4
EBI SRAM CS2
EBI SRAM CS3
EBI SRAM/SDRAM CS1
EBI SRAM CS5
Internal SRAM 0
Internal SRAM1
LCDC configuration
DMACA configuration
USBA Data
PBA
PBB
AT32AP7002
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