AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 45

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32054FS–AVR32–09/09
30. USART - TXD signal is floating in Modem and Hardware Handshaking mode
31. PWM - Impossible to update a period equal to 0 by using the CUPD register
32. WDT Clear is blocked after WDT Reset
33. USART - The DCD Signal is active high from the USART, but should be active low
34. MCI Transmit Data Register (TDR) FIFO corruption
TCMR.START = Receive start
RFMR.FSOS = None (Input)
RCMR.START = any on RF (edge/level)
Fix/Workaround
None.
The TXD signal is floating in Modem and Hardware Handshaking mode, but should be
pulled up.
Fix/Workaround
Enable pullup on this line in the PIO.
It is impossible to UPDATE a period equal to 0 by the using of the UPDATE register
(CUPD).
Fix/Workaround
To update a period equal to 0, write directly to the CPRD register.
A watchdog timer event will, after reset, block writes to the WDT_CLEAR register, prevent-
ing the program to clear the next Watchdog Timer Reset.
Fix/Workaround
If the RTC is not used a write to AVR32_RTC.ctrl.pclr = 1, instead of writing to
AVR32_WDT.clr, will reset the prescaler and thus prevent the watchdog event from happen-
ing. This will render the RTC useless, but prevents WDT reset because the RTC and WDT
share the same prescaler. Another sideeffect of this is that the watchdog timeout period will
be half the expected timeout period.
If the RTC is used one can disable the Watchdog Timer (WDT) after a WDT reset has
occured. This will prevent the WDT resetting the system. To make the WDT functional again
a hard reset (power on reset or RESET_N) must be applied. If you still want to use the WDT
a f t e r a W D T r e s e t a s m a l l c o d e c a n b e i n s e r te d a t t h e s ta r tu p c h e c k i n g t h e
AVR32_PM.rcause register for WDT reset and use a GPIO pin to reset the system. This
method requires that one of the GPIO pins are available and connected externally to the
RESET_N pin. After the GPIO pin has pulled down the reset line the GPIO will be reset and
leave the pin tristated with pullup.
The DCD signal is active high from the USART, but should be active low.
Fix/Workaround
An inverter should be added on this line on the PCB.
If the number of bytes to be transmitted by the MCI is not a multiple of 4, the Transmit Data
Register (TDR) First In First Out data buffer control logic will become corrupted when trans-
mit data is written to the TDR as 32-bit values.
Fix/Workaround
AT32AP7002
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