AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet
AT32AP7002-CTUT
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AT32AP7002-CTUT Summary of contents
Page 1
... On-Chip Debug System – Nexus Class 3 – Full speed, non-intrusive data and program trace – Runtime control and JTAG interface • Package/Pins – AT32AP7002: 196-ball CTBGA • Power supplies – 1.65V to1.95V VDDCORE – 3.0V to 3.6V VDDIO ® 32 32-Bit Microcontroller ® ...
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... AT32AP7002 also features an onboard LCD Controller, supporting single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays gray shades are supported using a time-based dither- ing algorithm and Frame Rate Control (FRC) method ...
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... AT32AP7002 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The C-compiler is closely linked to the architecture and is able to utilize code optimization fea- tures, both for size and speed. 32054F–AVR32–09/09 ...
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... Ground Ground Ground Ground Clocks, Oscillators, and PLL’s Analog Analog Analog JTAG Input Input Output Input Input Auxiliary Port - AUX Output Output Output Input AT32AP7002 Active Level Comments 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 3.0 to 3.6V Low Low 4 ...
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... AC97 Controller - AC97C Input Output Output Input Audio Bitstream DAC - ABDAC Output Output External Bus Interface - EBI I/O Output Output Output Output Output I/O Output Output Output AT32AP7002 Active Level Comments Low Low Low Low Low Low Low Low Low Low Low 5 ...
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... Output Output Output Output Image Sensor Interface - ISI Input Input Input Input LCD Controller - LCDC Output Input Output Output Output Output Output Output Output MultiMedia Card Interface - MCI Output I/O AT32AP7002 Active Level Comments Low Low Low Low Low Low Low 6 ...
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... Type Parallel Input/Output - PIOA, PIOB, PIOC, PIOD PS2 Interface - PSIF Serial Peripheral Interface - SPI0, SPI1 Output Synchronous Serial Controller - SSC0, SSC1, SSC2 Output DMA Controller - DMACA Timer/Counter - TIMER0, TIMER1 AT32AP7002 Active Level Comments I/O I/O I/O I/O I/O Input ...
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... Input Input Input Two-wire Interface - TWI I/O I/O I/O Input Output Input Output Pulse Width Modulator - PWM Output USB Interface - USBA Analog Analog Analog Analog Analog AT32AP7002 Active Level Comments Connected to a 6810 Ohm ± 0.5% resistor to gound and capacitor to ground. 8 ...
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... Power Considerations 3.1 Power Supplies The AT32AP7002 has several types of power supply pins: • VDDCORE pins: Power the core, memories, and peripherals. Voltage is 1.8V nominal. • VDDIO pins: Power I/O lines. Voltage is 3.3V nominal. • VDDPLL pin: Powers the PLL. Voltage is 1.8V nominal. ...
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... TCK EVTI_N PB24 PA00 VDDIO GND PA12 PA16 GND PA19 GND VDDIO PA23 PD17 AVDDUSB PD12 PD15 PD16 PD13 PD14 XIN1 AT32AP7002 BOTTOM VIEW PC23 PC20 XIN32 PC22 XOUT32 PC29 XOUT0 AGNDOSC AVDDOSC OSCEN_N TDI RESET_N PA02 PA08 PA10 PA14 PA09 ...
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... PB13 PB00 PX44 GND PX43 PX31 VDDIO PX28 PX29 PX23 PX27 PX36 PX19 PX07 VDDIO PX11 PX12 PX09 PB29 PX52 PX08 AT32AP7002 13 14 PB05 PB04 PB06 PB03 PB07 PB02 GND PB01 VDDIO PX45 PX46 PX40 VDDCORE PX39 VDDCORE PX26 PX21 PX24 ...
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... HSB-PB HSB-PB BRIDGE BRIDGE DMA CONTROLLER DAC INTERFACE POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER EXTERNAL INTERRUPT CONTROLLER AT32AP7002 PIXEL COPROCESSOR VSYNC, DATA HSYNC, CACHE LCD PWR, PCLK, CONTRO MODE, LLER DVAL, CC, DATA[22..0], GPL[7.. DMA M RAS, CAS, SDWE, ...
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... Supports subsampled input color spaces (i.e 4:2:2, 4:2:0). • Configurable Filter Coefficients. • Throughput of one sample per cycle for a 9-tap FIR filter. • Can use the built-in accumulator to extend the FIR filter to more than 9-taps. • Can be used for bilinear/bicubic interpolations. AT32AP7002 13 ...
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... HSB bus matrix with 10 Masters and 8 Slaves handled – Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller, LCD Controller, DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM EBI and, USB. 32054F–AVR32–09/09 AT32AP7002 14 ...
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... Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the HSB bus, and which DMA controller is connected to which peripheral. 32054F–AVR32–09/09 AT32AP7002 Figure 4-1 on page 12. All modules connected to the accessed default ...
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... All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, I/O lines default as inputs with pull-up resistors enabled, except when indicated otherwise in the column “Reset State” of the PIO Controller multiplexing tables. 32054F–AVR32–09/09 AT32AP7002 16 ...
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... The AVR32 AP CPU AVR32 AP targets high-performance applications, and provides an advanced OCD system, effi- cient data and instruction caches, and a full MMU. of AVR32 AP. 32054F–AVR32–09/09 AT32AP7002 Figure 6-1 on page 18 displays the contents 17 ...
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... Overview of the AVR32 AP CPU OCD system AVR32 CPU pipeline with Java accelerator MMU Dcache controller HSB master shows an overview of the AVR32 AP pipeline stages. AT32AP7002 JTAG Reset control control BTB RAM interface Icache controller Cache RAM interface HSB master ...
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... Instruction and data accesses perform lookups in the micro-TLBs. If the access misses in the micro-TLBs, an access in the common TLB is per- formed. If this access misses, a page miss exception is issued. 32054F–AVR32–09/09 The AVR32 AP Pipeline IF2 ID IS Decode unit AT32AP7002 M1 M2 Multiply pipe ALU pipe Load-store ...
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... AVR32 AP Technical Reference Manual for details. Table 6-1. Instruction ld.w st.w lddsp lddpc stdsp ld.d st.d All coprocessor memory access instruction 32054F–AVR32–09/09 Instructions with unaligned reference support Supported alignment Any Any Any Any Any Word Word Word AT32AP7002 20 ...
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... An inter- rupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. The addresses and priority of simultaneous events are shown in 32054F–AVR32–09/09 AT32AP7002 Table 6-2 on page 22. 21 ...
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... DTLB DTLB Miss (Write) DTLB DTLB Protection (Read) DTLB DTLB Protection (Write) DTLB DTLB Modified DTLB AT32AP7002 Stored Return Address Undefined First non-completed instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction ...
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... RAR_INT0 RAR_INT1 RAR_SUP and Figure 6-5 on page 24. The lower word contains the and Q condition The Status Register High Halfword AT32AP7002 Figure 6-3 on page 23 shows the model used INT2 INT3 Bit 0 Bit 31 Bit 0 Bit 31 Bit LR_INT3 SP_SYS SP_SYS R12 R12 R12_INT3 R11 ...
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... Overview of execution modes, their priorities and privilege levels. Mode Security Non Maskable Interrupt Privileged Exception Privileged Interrupt 3 Privileged Interrupt 2 Privileged Interrupt 1 Privileged Interrupt 0 Privileged Supervisor Privileged Application Unprivileged AT32AP7002 Bit Bit name Initial value Carry Zero Sign Overflow Saturation Lock ...
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... Debug state is exited by the retd instruction. 6.3.3.3 Java State AVR32 AP implements a Java Extension Module (JEM). The processor can be set in a Java State where normal RISC operations are suspended. Refer to the AVR32 Java Technical Refer- ence Manual for details. 32054F–AVR32–09/09 AT32AP7002 25 ...
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... Supports subsampled input color spaces (i.e 4:2:2, 4:2:0). • Configurable Filter Coefficients. • Throughput of one sample per cycle for a 9-tap FIR filter. • Can use the built-in accumulator to extend the FIR filter to more than 9-taps. • Can be used for bilinear/bicubic interpolations. AT32AP7002 26 ...
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... INPIX0 INPIX1 Input Pixel Selector VMU0_IN2 VMU1_IN0 VMU1_IN1 COEFF1_0 COEFF1_1 VMU1 COEFF1_2 OFFSET1 VMU1_OUT ADD Output Pixel Inserter OUTPIX0 OUTPIX1 OUTPIX2 AT32AP7002 INPIX2 VMU1_IN2 VMU2_IN0 VMU2_IN1 COEFF2_0 COEFF2_1 VMU2 COEFF2_2 OFFSET2 VMU2_OUT Pipeline Stage 1 VMU2_IN2 Pipeline Stage 2 Pipeline Stage 3 27 ...
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... Inside VMUn (n ∈ {0,1,2}) coeffn_0 vmun_in0 Multiply VMU0_OUT COEFF0_0 COEFF0_1 COEFF0_2 = VMU1_OUT COEFF1_0 COEFF1_1 COEFF1_2 VMU2_OUT COEFF2_0 COEFF2_1 COEFF2_2 AT32AP7002 Figure 7-2 on page vmu_in0 + offset vmu_in1 vmu_in2 coeffn_1 vmun_in1 coeffn_2 vmun_in2 Multiply Multiply Vector Adder vmun_out ...
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... COEFF0_0 COEFF0_1 COEFF0_2 VMU1_OUT = COEFF1_0 COEFF1_1 COEFF1_2 VMU2_OUT = COEFF2_0 COEFF2_1 COEFF2_2 Vertical Filter Mode Pixel Addressing INPIX0 IN0 INPIX1 IN4 INPIX2 IN8 AT32AP7002 shows how the pixel triplet is found by taking the pixel IN1 IN2 IN3 IN5 IN6 IN7 IN9 IN10 IN11 IN(x+ ...
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... Figure 7-5 on page 30 and Table 7-2 on page Planar Pixel Insertion = VMU0 = VMU1 = VMU2 OUT0 OUT1 OUTPIX0 OUT4 OUT5 OUTPIX1 OUTPIX2 OUT8 OUT9 AT32AP7002 IN((x+0)%11 OFFSET0 or VMU0_OUT IN((x+4)%11) IN((x+8)%11) IN((y+0)%11 OFFSET1 or VMU1_OUT IN((y+4)%11) IN((y+8)%11) IN((z+0)%11) ( OFFSET2 or VMU2_OUT + IN((z+4)%11) IN((z+8)%11) 48 ...
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... Figure 7-6. Packed Pixel Insertion. = VMU0 = VMU1 = VMU2 OUTPIX0 OUT0 OUT1 OUT2 32054F–AVR32–09/09 OUTPIX1 OUT3 OUT4 OUT5 OUT6 AT32AP7002 Figure 7-6 on page 31 and Table 7-2 on page OUTPIX2 OUT7 OUT8 OUT9 48. The OUT10 OUT11 ...
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... Coefficient Register A for VMU2 cr11 Coefficient Register B for VMU2 cr12 Output from VMU0 cr13 Output from VMU1 cr14 Output from VMU2 cr15 PICO Configuration Register 32054F–AVR32–09/09 AT32AP7002 Name Access INPIX2 Read/Write INPIX1 Read/Write INPIX0 Read/Write OUTPIX2 Read Only OUTPIX1 ...
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... Input Pixel number 1 to the Input Pixel Selector Unit. • IN2: Input Pixel 2 Input Pixel number 2 to the Input Pixel Selector Unit. • IN3: Input Pixel 3 Input Pixel number 3 to the Input Pixel Selector Unit. 32054F–AVR32–09/ IN0 IN1 IN2 IN3 AT32AP7002 ...
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... Input Pixel number 5 to the Input Pixel Selector Unit. • IN2: Input Pixel 6 Input Pixel number 6 to the Input Pixel Selector Unit. • IN3: Input Pixel 7 Input Pixel number 7 to the Input Pixel Selector Unit. 32054F–AVR32–09/ IN4 IN5 IN6 IN7 AT32AP7002 ...
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... Input Pixel number 9 to the Input Pixel Selector Unit. • IN2: Input Pixel 10 Input Pixel number 10 to the Input Pixel Selector Unit. • IN3: Input Pixel 11 Input Pixel number 11 to the Input Pixel Selector Unit. 32054F–AVR32–09/ IN8 IN9 IN10 IN11 AT32AP7002 ...
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... Output Pixel number 1 from the Output Pixel Inserter Unit. • OUT2: Output Pixel 2 Output Pixel number 2 from the Output Pixel Inserter Unit. • OUT3: Output Pixel 3 Output Pixel number 3 from the Output Pixel Inserter Unit. 32054F–AVR32–09/ OUT0 OUT1 OUT2 OUT3 AT32AP7002 ...
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... Output Pixel number 5 from the Output Pixel Inserter Unit. • OUT6: Output Pixel 6 Output Pixel number 6 from the Output Pixel Inserter Unit. • OUT7: Output Pixel 7 Output Pixel number 7 from the Output Pixel Inserter Unit. 32054F–AVR32–09/ OUT4 OUT5 OUT6 OUT7 AT32AP7002 ...
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... Output Pixel number 9 from the Output Pixel Inserter Unit. • OUT10: Output Pixel 10 Output Pixel number 10 from the Output Pixel Inserter Unit. • OUT11: Output Pixel 11 Output Pixel number 11 from the Output Pixel Inserter Unit. 32054F–AVR32–09/ OUT8 OUT9 OUT10 OUT11 AT32AP7002 ...
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... COEFF0_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF0_1 is sign- extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 32054F–AVR32–09/ COEFF0_0 COEFF0_1 AT32AP7002 COEFF0_0 COEFF0_1 COEFF_FRAC_BITS ⁄ COEFF0_0 2 COEFF_FRAC_BITS ⁄ COEFF0_1 2 ...
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... OFFSET_FRAC_BITS ⁄ , where the OFFSET0 value is interpreted as a 2’s complement integer. When reading this reg- OFFSET0 2 ister, OFFSET0 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 32054F–AVR32–09/ COEFF0_2 OFFSET0 AT32AP7002 COEFF0_2 OFFSET0 COEFF_FRAC_BITS ⁄ COEFF0_2 ...
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... COEFF1_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF1_1 is sign- extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 32054F–AVR32–09/ COEFF1_0 COEFF1_1 AT32AP7002 COEFF1_0 COEFF1_1 COEFF_FRAC_BITS ⁄ COEFF1_0 2 COEFF_FRAC_BITS ⁄ COEFF1_1 2 ...
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... OFFSET_FRAC_BITS ⁄ , where the OFFSET1 value is interpreted as a 2’s complement integer. When reading this reg- OFFSET1 2 ister, OFFSET1 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 32054F–AVR32–09/ COEFF1_2 OFFSET1 AT32AP7002 COEFF1_2 OFFSET1 COEFF_FRAC_BITS ⁄ COEFF1_2 ...
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... COEFF2_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF2_1 is sign- extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 32054F–AVR32–09/ COEFF2_0 COEFF2_1 AT32AP7002 COEFF2_0 COEFF2_1 COEFF_FRAC_BITS ⁄ COEFF2_0 2 COEFF_FRAC_BITS ⁄ COEFF2_1 2 ...
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... OFFSET_FRAC_BITS ⁄ , where the OFFSET2 value is interpreted as a 2’s complement integer. When reading this reg- OFFSET2 2 ister, OFFSET2 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 32054F–AVR32–09/ COEFF2_2 OFFSET2 AT32AP7002 COEFF2_2 OFFSET2 COEFF_FRAC_BITS ⁄ COEFF2_2 ...
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... The output from VMU0 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is sign- extended to 32-bits. 32054F–AVR32–09/ VMU0_OUT VMU0_OUT AT32AP7002 VMU0_OUT ...
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... The output from VMU1 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is sign- extended to 32-bits. 32054F–AVR32–09/ VMU1_OUT VMU1_OUT AT32AP7002 VMU1_OUT ...
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... The output from VMU2 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is sign- extended to 32-bits. 32054F–AVR32–09/ VMU2_OUT VMU2_OUT AT32AP7002 VMU2_OUT ...
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... Each of the OUTPIXn registers will get one of the resulting pixels. The triplet address specifies what byte in each of the OUTPIXn registers the results will be written to. OUT ← Scaled and saturated output from VMU0 OUT(d+ 4) ← Scaled and saturated output from VMU1 OUT ← Scaled and saturated output from VMU2 AT32AP7002 ...
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... Pixel triplets are selected for input to each of the VMUs by addressing horizontal pixel triplets from the INPIXn registers. Pixel triplets are selected for input to each of the VMUs by addressing vertical pixel triplets from the INPIXn registers. N.A AT32AP7002 for a description of the Input Pixel 49 ...
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... This ordering is reversed in comparison with how data is organized in memory (where the most significant part would receive the lowest address) and is intentional. 32054F–AVR32–09/09 Section 7.7.1 ”Register File” on page 32 AT32AP7002 for a complete list of registers. Table 7-1 on page 32 50 ...
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... Operations ASR(x, n) SE(x, Bits( >> n SATSU(x, n) Signed to Unsigned Saturation ( x is treated as a signed value ): > (2 -1)) then (2 SE(x, n) Sign Extend n-bit value 7.8.1.3 Data Type Extensions .d Double (64-bit) operation. .w Word (32-bit) operation. 32054F–AVR32–09/09 n-1 -1); elseif ( x < then 0; else x; AT32AP7002 51 ...
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... Store PICO register Store PICO register with post-increment Store PICO register with indexed addressing Store multiple PICO registers AT32AP7002 Operation See PICO instruction set reference See PICO instruction set reference See PICO instruction set reference See PICO instruction set reference PrHi:PrLo ← ...
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... OUT(d ← SATSU(ASR(VMU0_OUT + VMU1_OUT + VMU2_OUT, COEFF_FRAC_BITS) , 8); OUT(d ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT(d ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then OUT ← SATSU(ASR(VMU0_OUT + VMU1_OUT+ VMU2_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); 32054F–AVR32–09/09 AT32AP7002 IN(x+0) + VMU0_OUT IN(x+1) IN(x+2) IN(y+0) + ...
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... VMU0_OUT = c0*src[0]+c1*src[1]+c2*src[2] + 0.5 VMU1_OUT = c3*src[3]+c4*src[4]+c5*src[5] VMU2_OUT = c6*src[6]+c7*src[ INPIX1={src[15],src[14],src[13],src[12]}, INPIX2 ={src[11],src[10],src[9],src[8 VMU0_OUT += c0*src[15]+c1*src[14]+c2*src[13] VMU1_OUT += c3*src[12]+c4*src[11]+c5*src[10] VMU2_OUT += c6*src[9]+c7*src[8] OUT3 = satscaled(VMU0_OUT+VMU1_OUT+VMU2_OUT)*/ /* src OUT0, OUT1, OUT2, OUT3 } /* *dst = OUT3 */ AT32AP7002 ...
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... OUT(d ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT(d ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then OUT ← SATSU(ASR(VMU0_OUT + VMU1_OUT+ VMU2_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); 32054F–AVR32–09/09 AT32AP7002 IN(x+0) + OFFSET0 << OFFSET_SCALE IN(x+1) IN(x+2) IN(y+0) OFFSET1 < ...
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... OUT0 = A*src[j][i+0] + B*src[j][i+1] C*src[j+1][i] + D*src[j+1][i+ OUT1 = A*src[j][i+1] + B*src[j][i+2] C*src[j+1][i+1] + D*src[j+1][i+ INPIX1 = r3, INPIX2 = OUT2 = A*src[j][i+2] + B*src[j][i+3] C*src[j+1][i+2] + D*src[j+1][i+ OUT3 = A*src[j][i+3] + B*src[j][i+4] C*src[j+1][i+3] + D*src[j+1][i+ src+= *((int *)src OUT0, OUT1, OUT2, OUT3 } */ AT32AP7002 ...
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... OUT(d ← SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8); OUT(d ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT(d ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then OUT ← SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); 32054F–AVR32–09/09 AT32AP7002 IN(x+0) + VMU0_OUT IN(x+1) IN(x+2) IN(y+0) + ...
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... VMU1_OUT = c0*src[0][1]+c1*src[1][1]+c2*src[2][1] + 0.5 VMU2_OUT = c0*src[0][2]+c1*src[1][2]+c2*src[2][2] + 0.5*/ /* INPIX2 = {src[3][0], src[3][1], src[3][2], src[3][3] }*/ /* INPIX1 = {src[4][0], src[4][1], src[4][2], src[4][3] }*/ /* INPIX0 = {src[5][0], src[5][1], src[5][2], src[5][3] }*/ /* VMU0_OUT += c0*src[5][0]+c1*src[4][0]+c2*src[3][0] VMU1_OUT += c0*src[5][1]+c1*src[4][1]+c2*src[3][1] VMU2_OUT += c0*src[5][2]+c1*src[4][2]+c2*src[3][2] OUT0 = satscale(VMU0_OUT), OUT1 = satscale(VMU1_OUT), OUT2 = satscale(VMU2_OUT) */ AT32AP7002 ...
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... OUT(d ← SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8); OUT(d ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT(d ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then OUT ← SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8); OUT ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); 32054F–AVR32–09/09 AT32AP7002 IN(x+0) + OFFSET0 << OFFSET_SCALE IN(x+1) IN(x+2) IN(y+0) + OFFSET1 < ...
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... INx /* INPIX0= { Y[0], Y[1], Y[2], Y[3] }*/ /* INPIX1= { Cr[0], Cr[1], Cr[2], Cr[3] }*/ /* INPIX2= { Cb[0], Cb[1], Cb[2], Cb[3] }*/ /* OUT0 = r[0], OUT1 = g[0], OUT2 = b[ OUT3 = r[1], OUT4 = g[1], OUT5 = b[ OUT6 = r[2], OUT7 = g[2], OUT8 = b[ OUT9 = r[3], OUT10 = g[3], OUT11 = b[3] */ AT32AP7002 INy 17 16 OUT ...
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... Pr ∈ { INPIX0, INPIX1, INPIX2, COEFF0_A, COEFF0_B, COEFF1_A, COEFF1_B, COEFF2_A, IV-VI. COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG} I-II, IV-V.p ∈ {0, 1, …, 15} disp ∈ {0, 4, …, 1020} I, IV. III, VI. {b, i} ∈ {0, 1, …, 15} III, VI. sa ∈ { Opcode PICO CP PICO CP# 0 32054F–AVR32–09/ PrLo[3: PrLo[3: AT32AP7002 disp8 ...
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... III PICO CP PICO CP PICO CP PICO CP# 1 Example: picold.d COEFF0_B:COEFF0_A, r12[4] 32054F–AVR32–09/ PrLo[3: AT32AP7002 Shamt disp8 Shamt ...
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... INPIX1 ← *(Loadaddress++); if ( PICORegList contains INPIX2) INPIX2 ← *(Loadaddress++); if Opcode[++] == 1 then Rp ← Loadaddress; Syntax: I. picoldm Rp{++}, PICORegList II. picoldm Rp{++}, PICORegList III. picoldm Rp{++}, PICORegList Operands: PICORegList ∈ { {INPIX1, INPIX2}, {OUTPIX2, INPIX0}, {OUTPIX0, OUTPIX1}, {COEFF0_B, COEFF0_A}, I. {COEFF1_B, COEFF1_A}, {COEFF2_B, COEFF2_A}, {VMU1_OUT, VMU0_OUT}, 32054F–AVR32–09/09 AT32AP7002 63 ...
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... III. picoldm r12, VMU0_OUT, VMU1_OUT, VMU2_OUT 32054F–AVR32–09/ CONFIG VMU1_OUT COEFF2_B 0 VMU2_OUT VMU0_OUT COEFF2_A COEFF0_B COEFF0_A OUTPIX0 CONFIG VMU2_OUT VMU1_OUT AT32AP7002 COEFF1_B COEFF0_B OUTPIX0 OUTPIX2 COEFF1_A COEFF0_A OUTPIX1 INPIX0 OUTPIX1 OUTPIX2 INPIX0 INPIX1 VMU0_OUT COEFF2_B COEFF2_A COEFF1_B INPIX1 INPIX2 INPIX2 16 1 ...
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... Pr ∈ { INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B, COEFF1_A, II, IV. COEFF1_B, COEFF2_A, COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG} s ∈ { …, 14 ∈ { …, 14} III. s ∈ {0, 1, …, 15} II. d ∈ {0, 1, …, 15} IV. Opcode PICO CP PICO CP# 0 32054F–AVR32–09/ PrLo[3: AT32AP7002 ...
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... III PICO CP PICO CP# 0 Example: picomv.d r2, OUTPIX0:OUTPIX1 picomv.w CONFIG, lr 32054F–AVR32–09/ PrLo[3: AT32AP7002 ...
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... Pr ∈ { INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B, COEFF1_A, IV-VI. COEFF1_B, COEFF2_A, COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG} I-II, IV-V.p ∈ {0, 1, …, 15} disp ∈ {0, 4, …, 1020} I, IV. III, VI. {b, i} ∈ {0, 1, …, 15} III, VI. sa ∈ { Opcode PICO CP PICO CP# 0 32054F–AVR32–09/ PrLo[3: PrLo[3: AT32AP7002 disp8 ...
Page 68
... III PICO CP PICO CP PICO CP PICO CP# 1 Example: picost.w r10++, OUTPIX0 32054F–AVR32–09/ PrLo[3: AT32AP7002 Shamt disp8 Shamt ...
Page 69
... PICORegList contains INPIX1) *(Storeaddress++) ←INPIX1 ; if ( PICORegList contains INPIX2) *(Storeaddress++) ←INPIX2 ; Syntax: I. picostm {--}Rp, PICORegList II. picostm {--}Rp, PICORegList III. picostm {--}Rp, PICORegList Operands: PICORegList ∈ { {INPIX1, INPIX2}, {OUTPIX2, INPIX0}, {OUTPIX0, OUTPIX1}, {COEFF0_B, COEFF0_A}, I. {COEFF1_B, COEFF1_A}, {COEFF2_B, COEFF2_A}, {VMU1_OUT, VMU0_OUT}, 32054F–AVR32–09/09 AT32AP7002 69 ...
Page 70
... III. picostm r11, VMU0_OUT, VMU1_OUT, VMU2_OUT 32054F–AVR32–09/ CONFIG VMU1_OUT COEFF2_B 1 VMU2_OUT VMU0_OUT COEFF2_A COEFF0_B COEFF0_A OUTPIX0 CONFIG VMU2_OUT VMU1_OUT AT32AP7002 COEFF1_B COEFF0_B OUTPIX0 OUTPIX2 COEFF1_A COEFF0_A OUTPIX1 INPIX0 OUTPIX1 OUTPIX2 INPIX0 INPIX1 VMU0_OUT COEFF2_B COEFF2_A COEFF1_B INPIX1 INPIX2 INPIX2 16 1 ...
Page 71
... Pipeline Stage 2 and Pipeline Stage 3. picoldm Writes to INPIXn registers produces no hazard since they are only accessed in Pipeline Stage 1. picomv.x Rd,... Read-After-Write Hazard (RAW) will occur if reading picost.x the PICO register file while a command is in the picostm pipeline. AT32AP7002 Stall Cycles ...
Page 72
... Physical Memory Map The system bus is implemented as an HSB bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AT32AP7002 by default uses segment translation, as described in the AVR32 Architecture Manual. The 32 bit physical address space is mapped as follows: Table 8-1 ...
Page 73
... Table 8-3. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 32054F–AVR32–09/09 HSB masters HSB slaves AT32AP7002 CPU Dcache CPU Icache HSB-HSB Bridge ISI DMA USBA DMA LCD Controller DMA DMAC Master Interface 0 DMAC Master Interface 1 Internal SRAM 0 Internal SRAM1 PBA ...
Page 74
... Universal Synchronous Asynchronous Receiver USART3 Transmitter - USART3 SSC0 Synchronous Serial Controller - SSC0 SSC1 Synchronous Serial Controller - SSC1 SSC2 Synchronous Serial Controller - SSC2 PIOA Parallel Input/Output 2 - PIOA PIOB Parallel Input/Output 2 - PIOB PIOC Parallel Input/Output 2 - PIOC PIOD Parallel Input/Output 2 - PIOD AT32AP7002 Bus HSB HSB HSB ...
Page 75
... ABDAC Audio Bitstream DAC - ABDAC MCI MultiMedia Card Interface - MCI AC97C AC97 Controller - AC97C ISI Image Sensor Interface - ISI USBA USB Configuration Interface - USBA SMC Static Memory Controller - SMC SDRAMC SDRAM Controller - SDRAMC ECC Error Correcting Code Controller - ECC AT32AP7002 Bus ...
Page 76
... Each group can have interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individ- ual submodules for a description of the semantic of the different interrupt requests. The interrupt request signals in AT32AP7002 are connected to the INTC as follows: Table 9-2. Group ...
Page 77
... EXTERNAL DMA REQUEST 1 EXTERNAL DMA REQUEST 2 EXTERNAL DMA REQUEST 3 32054F–AVR32–09/09 Interrupt Request Signal Map Line Signal 0 EIC0 1 EIC1 2 EIC2 3 EIC3 RTC 0 TC00 1 TC01 2 TC02 0 TC10 1 TC11 2 TC12 0 PWM 0 ABDAC 0 MCI 0 AC97C 0 ISI 0 USBA 0 EBI Hardware Handshaking Connection AT32AP7002 Hardware Handshaking Interface ...
Page 78
... XC0 XC1 XC2 Internal TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 USART clock connections Source Name Internal CLK_DIV AT32AP7002 Connection clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 9.7 clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 9.7 Connection clk_pba / 8 78 ...
Page 79
... SPI clock connections Source Internal External Interrupt Pin Mapping Nexus OCD AUX port connections AXS=0 EVTI_N PB09 PB08 PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00 AT32AP7002 Name Connection CLK_DIV clk_pba / 32 Connection PB24 PB25 PB26 PB27 PB28 AXS=1 EVTI_N PC18 PC14 PC12 PC11 ...
Page 80
... Peripheral Multiplexing on IO lines The AT32AP7002 features five PIO controllers, PIOA to PIOE, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions The tables in the following pages define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers ...
Page 81
... PB24 NMI_N PB25 EXTINT0 PB26 EXTINT1 PB27 EXTINT2 PB28 EXTINT3 PB29 PM - GCLK[3] PB30 PM - GCLK[4] AT32AP7002 TC1 - B2 TC1 - CLK1 TC1 - CLK2 Peripheral B SPI1 - MISO SPI1 - MOSI SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - SCK MCI - CMD[1] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] ...
Page 82
... AT32AP7002 82 ...
Page 83
... LCDC - DATA[7] PD04 LCDC - DATA[10] PD05 LCDC - DATA[11] PD06 LCDC - DATA[12] PD07 LCDC - DATA[13] PD08 LCDC - DATA[14] PD09 LCDC - DATA[15] PD12 LCDC - DATA[18] PD13 LCDC - DATA[19] PD14 LCDC - DATA[20] PD15 LCDC - DATA[21] PD16 LCDC - DATA[22] PD17 LCDC - DATA[23] AT32AP7002 Peripheral B Peripheral B 83 ...
Page 84
... Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. 32054F–AVR32–09/09 HMATRIX_SFR4 Read/Write – – – – – – – – – EBI_CS4A EBI_CS3A AT32AP7002 – – – – – – – – EBI_DBPUC – EBI_CS1A - 84 ...
Page 85
... EBI - DATA[14] EBI - DATA[15] EBI - ADDR[0] EBI - ADDR[1] EBI - ADDR[2] EBI - ADDR[3] EBI - ADDR[4] EBI - ADDR[5] EBI - ADDR[6] EBI - ADDR[7] EBI - ADDR[8] EBI - ADDR[9] EBI - ADDR[10] EBI - ADDR[11] EBI - ADDR[12] EBI - ADDR[13] EBI - ADDR[14] EBI - ADDR[15] AT32AP7002 The pull-up resistors are 85 ...
Page 86
... EBI - ADDR[18] EBI - ADDR[19] EBI - ADDR[20] EBI - ADDR[21] EBI - ADDR[22] EBI - NCS[0] EBI - NCS[1] EBI - NCS[3] EBI - NRD EBI - NWE0 EBI - NWE1 EBI - NWE3 EBI - SDCK EBI - SDCKE EBI - RAS EBI - CAS EBI - SDWE EBI - SDA10 EBI - NANDOE EBI - NANDWE AT32AP7002 86 ...
Page 87
... Programming Facilities – Word, Half-word, Byte Access – Automatic Page Break When Memory Boundary Has Been Reached – Multibank Ping-pong Access – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable 32054F–AVR32–09/09 AT32AP7002 TM TM and CompactFlash Support TM Support ...
Page 88
... The chip select line may be left active to speed up transfers on the same device 9.8.6 Two-wire Interface • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations 32054F–AVR32–09/09 AT32AP7002 ™ Devices with 8- or 16-bit Data Path. 88 ...
Page 89
... One RX and one TX channel for data transfers, connected to the DMACA • Time Slot Assigner allowing to assign time slots to a channel • Channels support mono or stereo bit sample length - Variable sampling rate AC97 Codec Interface (48KHz and below) 32054F–AVR32–09/09 AT32AP7002 89 ...
Page 90
... Two independent Linear Dividers working on modulo n counter outputs • Independent channel programming – Independent Enable Disable Commands – Independent Clock – Independent Period and Duty Cycle, with Double Bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 32054F–AVR32–09/09 AT32AP7002 90 ...
Page 91
... Controller for management of virtual Frame Buffer – Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer • Automatic resynchronization of the frame buffer pointer to prevent flickering • Configurable coefficients with flexible fixed-point representation. 32054F–AVR32–09/09 AT32AP7002 91 ...
Page 92
... Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image 50 • Programmable frame capture rate 32054F–AVR32–09/09 AT32AP7002 92 ...
Page 93
... CPU. The system will return to normal on occurence of interrupts or an event on the WAKE_N pin. The Power Manager also cointains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identifed by software. 32054F–AVR32–09/09 AT32AP7002 93 ...
Page 94
... Power-On Detector Soft reset sources 32054F–AVR32–09/09 Synchronous Clock Generator PLL0 PLL1 Generic Clock Generator 32 KHz OSC/PLL Oscillator Control signals Oscillator and Startup PLL Control Counter Sleep Sleep Controller instruction Reset Controller resets AT32AP7002 Synchronous clocks Generic clocks Slow clock 94 ...
Page 95
... See Electrical Characteristics for the allowed frequency range. The main Section 10.5.6 on page 101. After a power-on reset, or when waking up from a (1) The PM masks the main oscillator outputs during this start- Figure 10-1. The 32 KHz oscillator ultra-low power design, and AT32AP7002 Section 10.5.6 on page ...
Page 96
... PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable. 32054F–AVR32–09/09 AT32AP7002 96 ...
Page 97
... Characteristics chapter. The input frequency for the PLL relates to the oscillator frequency and PLLDIV setting as follows: f PLLIN 32054F–AVR32–09/09 PLLMUL Output Divider PLLDIV PLL Input Divider PLLEN PLLOPT LFT (PLLMUL+1) / (PLLDIV+1) • f OSC = 2 • (PLLDIV+1)• OSC AT32AP7002 Mask PLL clock LOCK Lock Suppression PLLCOUNT 97 ...
Page 98
... To use PLLn, a passive RC filter should be connected to the LFTn pin, as shown in Filter values depend on the PLL reference and output frequency range. Atmel provides a tool named “Atmel PLL LFT Filter Calculator AT91”. The PLL for AT32AP7002 can be selected in this tool by selecting “AT91RM9200 (58A07F)” and leave “Icp = ‘1’” (default). ...
Page 99
... Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PB bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. 32054F–AVR32–09/09 (CPUSEL+ main contains a list of implemented maskable clocks. AT32AP7002 Also, fre- CPU HSB PBA,B 99 ...
Page 100
... When writing either mask register with any value, this bit is cleared. The bit is set when the clocks have been enabled and disabled according to the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the MSKRDY bit in IER. 32054F–AVR32–09/09 AT32AP7002 100 ...
Page 101
... Table 10-1. Maskable module clocks in AT32AP7002. Bit CPUMASK 0 PICO 31:17 - 10.5.6 Sleep modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument ...
Page 102
... If a 32054F–AVR32–09/09 Sleep modes Sleep Mode CPU HSB Idle Off On Frozen Off Off Standby Off Off Stop Off Off Static Off Off AT32AP7002 Table 10-2. PBA,B + Osc0,1 + Osc32 + GCLK PLL0,1 RTC/WDT Off On On Off Off On ...
Page 103
... Oscillator PLL0 source, as selected by the PLLSEL and OSCSEL bits. The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV, resulting in the output frequency: f GCLK 32054F–AVR32–09/09 0 Divider 1 PLLSEL DIV OSCSEL = f / (2*(DIV+1)) SRC AT32AP7002 Sleep Controller 0 Mask Generic Clock 1 DIVEN CEN 103 ...
Page 104
... When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition. 10.5.7.4 Generic clock implementation In AT32AP7002, there are 8 generic clocks. These are allocated to different functions as shown in Table Table 10-3. Clock number 10 ...
Page 105
... Debug qualified PB clocks are stopped during debug operation. The debug system can option- ally keep these clocks running during the debug operation. This is described in the documentation for the On-Chip Debug system. 32054F–AVR32–09/09 AT32AP7002 105 ...
Page 106
... JTAG Reset Register. See JTAG documentation for details. 32054F–AVR32–09/09 lists these and other reset sources supported by the Reset Controller. Detector Controller NTAE DBR Watchdog Reset AT32AP7002 RC_RCAUSE Soft Reset Reset Hard Reset CPU, HSB, PBA, PBB OCD, RTC/WDT ...
Page 107
... Watchdog Timer OCD 32054F–AVR32–09/09 Reset types Description Supply voltage below the power-on reset detector threshold voltage RESET_N pin asserted See On-Chip Debug documentation. See watchdog timer documentation. See On-Chip Debug documentation AT32AP7002 Type Hard Hard Soft Soft Soft 107 ...
Page 108
... Generic Clock Control 7 0x80 - 0xBC 0xC0 32054F–AVR32–09/09 Register Clock Select PLL0 Control PLL1 Control Interrupt Enable Interrupt Mask Interrupt Status Interrupt Clear Reserved Reset Cause AT32AP7002 Register Name Access MCCTRL Read/Write CKSEL Read/Write CPUMASK Read/Write HSBMASK Read/Write PBAMASK Read/Write PBBMASK ...
Page 109
... Main Clock Control Name: MCCTRL Access Type: Read/Write • PLLSEL: PLL Select 0: Oscillator 0 is source for the main clock 1: PLL0 is source for the main clock 32054F–AVR32–09/ AT32AP7002 PLLSEL - 109 ...
Page 110
... Note that if xxxDIV is written to 0, xxxSEL should also be written ensure correct operation. Also note that writing this register clears ISR:CKRDY. The register must not be re-written until CKRDY goes high. 32054F–AVR32–09/ (PBBSEL+1) . (PBASEL+1) . (HSBSEL+1) . (CPUSEL+1) . AT32AP7002 PBBSEL PBASEL HSBSEL CPUSEL 110 ...
Page 111
... If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is implementation dependent. 32054F–AVR32–09/ MASK[31:24 MASK[23:16 MASK[15: MASK[7:0] AT32AP7002 111 ...
Page 112
... Other values are reserved. • PLLOSC: PLL Oscillator Select 0: Oscillator 0 is the source for the PLL. 1: Oscillator 1 is the source for the PLL. • PLLEN: PLL Enable 0: PLL is disabled. 1: PLL is enabled. 32054F–AVR32–09/ PLLCOUNT PLLMUL PLLDIV PLLOPT OSC AT32AP7002 PLLOSC PLLEN 112 ...
Page 113
... The PLL is locked, and can be used as clock source. The effect of writing or reading the bits listed above depends on which register is being accessed: • IER (Write-only effect 1: Enable Interrupt • IDR (Write-only effect 1: Disable Interrupt 32054F–AVR32–09/ CKRDY VMRDY VOK AT32AP7002 WAKE LOCK1 LOCK0 113 ...
Page 114
... IMR (Read-only) 0: Interrupt is disabled 1: Interrupt is enabled • ISR (Read-only interrupt event has occurred 1: An interrupt even has not occurred • ICR (Write-only effect 1: Clear interrupt event 32054F–AVR32–09/09 AT32AP7002 114 ...
Page 115
... Oscillator is source for the generic clock. 1: PLL is source for the generic clock. • OSCSEL: Oscillator Select 0: Oscillator (or PLL source for the generic clock. 1: Oscillator (or PLL) 1is source for the generic clock. 32054F–AVR32–09/ DIV[7: DIVEN - AT32AP7002 CEN PLLSEL OSCSEL 115 ...
Page 116
... This bit is set if a reset occurred due to a timeout of the Watchdog Timer. • EXT: External Reset This bit is set if a reset occurred due to assertion of the RESET_N pin. • POR: Power-On Detector This bit is set if a reset was caused by the Power-On Detector. 32054F–AVR32–09/ SERP JTAG WDT AT32AP7002 EXT - POR 116 ...
Page 117
... Optionally, the RTC can wrap at a lower value, producing accurate periodic interrupts. 11.3 Block Diagram Figure 11-1. Real Time Counter module block diagram 16-bit Prescaler 32 KHz 11.4 Product Dependencies 11.4.1 I/O Lines None. 32054F–AVR32–09/09 RTC_TO P 32-bit counter TO PI RTC_VAL AT32AP7002 IRQ 117 ...
Page 118
... Writing the TOPI bit in IER enables the RTC interrupt, while writing the corresponding bit in IDR disables the RTC interrupt. IMR can be read to see whether or not the interrupt is enabled. If enabled, an interrupt will be generated if the TOPI flag in ISR is set. The flag can be cleared by writing TOPI in ICR to one. 32054F–AVR32–09/09 -(PSEL+ 32KHz AT32AP7002 118 ...
Page 119
... RTC Interrupt Disable 0x18 RTC Interrupt Mask 0x1C RTC Interrupt Status 0x20 RTC Interrupt Clear 32054F–AVR32–09/09 Register Register Name RTC Control RTC Value RTC Top AT32AP7002 Access CTRL Read/Write VAL Read/Write TOP Read/Write IER Write-only IDR Write-only IMR Read-only ...
Page 120
... TOPEN: Top Enable 0: RTC wraps at 0xFFFFFFFF 1: RTC wraps at RTC_TOP • PCLR: Prescaler Clear Writing this strobe clears the prescaler. Note that this also resets the watchdog timer. • EN: Enable 0: RTC is disabled 1: RTC is enabled 32054F–AVR32–09/ AT32AP7002 PSEL[3: TOPEN PCLR EN 120 ...
Page 121
... RTC Value Name: VAL Access Type: Read/Write • VAL: RTC Value This value is incremented on every rising edge of the source clock. 32054F–AVR32–09/ VAL[31:24 VAL[23:16 VAL[15: VAL[7:0] AT32AP7002 121 ...
Page 122
... RTC Top Name: TOP Access Type: Read/Write • TOP: RTC Top Value VAL wraps at this value if CTRL:TOPEN is 1. 32054F–AVR32–09/ TOP[31:24 TOP[23:16 TOP[15: TOP[7:0] AT32AP7002 122 ...
Page 123
... Interrupt is disabled 1: Interrupt is enabled • ISR (Read-only interrupt event has not occurred 1: An interrupt event has occurred. Note that this is only set when the RTC is configured to wrap at TOP. • ICR (Write-only effect 1: Clear interrupt event 32054F–AVR32–09/ AT32AP7002 TOPI 123 ...
Page 124
... WDT is enabled and the user tries to enter a sleepmode where the 32 KHz oscillator is turned off the system will enter the STOP sleepmode instead. This is to ensure the WDT is still running. 12.4.3 Debug Operation The watchdog timer is frozen during debug operation, unless the OCD system keeps peripherals running in debug operation. 32054F–AVR32–09/09 AT32AP7002 ...
Page 125
... The CLR register must be written with any value with regular intervals shorter than the watchdog timeout period. Otherwise, the device will receive a soft reset, and the code will start executing from the boot vector. 32054F–AVR32–09/09 (PSEL+ 30.518μs WDT AT32AP7002 125 ...
Page 126
... PSEL: Prescale Select Prescaler bit PSEL is used as watchdog timeout period. • EN: WDT Enable 0: WDT is disabled. 1: WDT is enabled. 32054F–AVR32–09/09 Register Register Name WDT Control WDT Clear KEY[7: AT32AP7002 Access CTRL Read/Write CLR Write-only PSEL[3: Reset 0x0 0x0 126 ...
Page 127
... WDT Clear Name: CLR Access Type: Write-only When the watchdog timer is enabled, this register must be periodically written, with any value, within the watchdog timeout period, to prevent a watchdog reset. 32054F–AVR32–09/09 AT32AP7002 127 ...
Page 128
... The interrupt requests from the peripherals (IREQn) and the NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure. 32054F–AVR32–09/09 gives an overview of the INTC. The grey boxes represent registers that can be AT32AP7002 128 ...
Page 129
... CPU status register, gets its corresponding ValReq line asserted. 32054F–AVR32–09/09 Interrupt Controller ValReqN GrpReqN OR . IPRn . . IRRn . . Request . Masking ValReq1 GrpReq1 OR IPR1 IRR1 ValReq0 GrpReq0 OR IPR0 IRR0 IPR Registers IRR Registers AT32AP7002 Masks INT_level, offset . INTLEVEL . . INT_level, AUTOVECTOR offset INT_level, offset ICR Registers CPU SREG Masks I[3-0]M GM 129 ...
Page 130
... This causes a pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared. 32054F–AVR32–09/09 AT32AP7002 130 ...
Page 131
... Interrupt Cause Register 3 0x204 Interrupt Cause Register 2 0x208 Interrupt Cause Register 1 0x20C Interrupt Cause Register 0 32054F–AVR32–09/09 Register Name ... IPR63 IRR0 IRR1 ... IRR63 ICR3 ICR2 ICR1 ICR0 AT32AP7002 Access IPR0 Read/Write IPR1 Read/Write ... ... Read/Write Read-only Read-only ... ... Read-only Read-only Read-only Read-only Read-only Reset ...
Page 132
... Indicates the EVBA-relative offset of the interrupt handler of the corresponding group: 00: INT0 01: INT1 10: INT2 11: INT3 • AUTOVECTOR: Autovector Address Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give halfword alignment. 32054F–AVR32–09/ AUTOVECTOR[13: AUTOVECTOR[7:0] AT32AP7002 132 ...
Page 133
... The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The IRRs are sampled continuously, and are read-only. 32054F–AVR32–09/ IRR[32*x+28] IRR[32*x+27 IRR[32*x+20] IRR[32*x+19 IRR[32*x+12] IRR[32*x+11 IRR[32*x+4] IRR[32*x+3] AT32AP7002 26 25 IRR[32*x+26] IRR[32*x+25] IRR[32*x+24 IRR[32*x+18] IRR[32*x+17] IRR[32*x+16 IRR[32*x+10] IRR[32*x+9] IRR[32*x+ IRR[32*x+2] IRR[32*x+1] IRR[32*x+ ...
Page 134
... Reset Value: N • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least one interrupt of level n is pending. 32054F–AVR32–09/ AT32AP7002 CAUSE 134 ...
Page 135
... PIO controller also possible to trigger the interrupt by driving these pins from registers in the PIO controller, or another peripheral out- put connected to the same pin. 32054F–AVR32–09/09 LEVEL ICR MODE Edge/Level INTn Detector ISR NMIC Mask NMI_IRQ AT32AP7002 IER IDR Mask IRQn IMR 135 ...
Page 136
... CPU has been set up to handle interrupts. Writing the EN bit in the NMIC register enables the NMI interrupt, while writing disables the NMI interrupt. When enabled, the interrupt trig- gers whenever the NMI_N pin is negated. The NMI_N pin is synchronized the same way as external level interrupts. 32054F–AVR32–09/09 AT32AP7002 136 ...
Page 137
... EIC Interrupt Clear 0x14 External Interrupt Mode 0x18 External Interrupt Edge 0x1C External Interrupt Level 0x24 External Interrupt NMI Control 32054F–AVR32–09/09 Register Register Name AT32AP7002 Access IER Write-only IDR Write-only IMR Read-only ISR Read-only ICR Write-only MODE Read/Write ...
Page 138
... IDR (Write-only effect 1: Disable Interrupt • IMR (Read-only) 0: Interrupt is disabled 1: Interrupt is enabled • ISR (Read-only interrupt event has occurred 1: An interrupt even has not occurred • ICR (Write-only effect 1: Clear interrupt event 32054F–AVR32–09/ INT3 AT32AP7002 INT2 INT1 INT0 138 ...
Page 139
... The bit interpretation is register specific: • MODE 0: Interrupt is edge triggered 1: Interrupt is level triggered • EDGE 0: Interrupt triggers on falling edge 1: Interrupt triggers on rising edge • LEVEL 0: Interrupt triggers on low level 1: Interrupt triggers on high level 32054F–AVR32–09/ INT3 AT32AP7002 INT2 INT1 INT0 139 ...
Page 140
... NMI Control Name: NMIC Access Type: Read/Write • EN: Enable 0: NMI disabled. Asserting the NMI pin does not generate an NMI request. 1: NMI enabled. Asserting the NMI pin generate an NMI request. 32054F–AVR32–09/ AT32AP7002 140 ...
Page 141
... HMATRIX before disabling the clock, to avoid freezing the HMATRIX in an undefined state. 15.4 Functional Description 15.4.1 Memory Mapping The Bus Matrix provides one decoder for every HSB Master Interface. The decoder offers each HSB Master several memory mappings. In fact, depending on the product, each memory area 32054F–AVR32–09/09 AT32AP7002 141 ...
Page 142
... The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for each slave: 1. Round-Robin Arbitration (default) 2. Fixed Priority Arbitration This choice is made via the field ARBT of the Slave Configuration Registers (SCFG). Each algorithm may be complemented by selecting a default master configuration for each slave. 32054F–AVR32–09/09 AT32AP7002 142 ...
Page 143
... Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer. 32054F–AVR32–09/09 143. See Section “•” on page 143. AT32AP7002 Section 15.4.3.1 ”Arbitration See Section “•” on page 143. 143 ...
Page 144
... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (PRAS and PRBS). 15.4.4 Slave and Master assignation The index number assigned to Bus Matrix slaves and masters are described in Memories chapter. 32054F–AVR32–09/09 AT32AP7002 144 ...
Page 145
... SCFG9 Read/Write SCFG10 Read/Write SCFG11 Read/Write SCFG12 Read/Write SCFG13 Read/Write SCFG14 Read/Write SCFG15 Read/Write PRAS0 Read/Write PRBS0 Read/Write PRAS1 Read/Write AT32AP7002 Reset Value 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000010 0x00000010 ...
Page 146
... PRBS14 Read/Write PRAS15 Read/Write PRBS15 Read/Write MRCR Read/Write SFR0 Read/Write SFR1 Read/Write SFR2 Read/Write SFR3 Read/Write SFR4 Read/Write SFR5 Read/Write AT32AP7002 Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ...
Page 147
... Special Function Register 15 32054F–AVR32–09/09 Name Access SFR6 Read/Write SFR7 Read/Write SFR8 Read/Write SFR9 Read/Write SFR10 Read/Write SFR11 Read/Write SFR12 Read/Write SFR13 Read/Write SFR14 Read/Write SFR15 Read/Write AT32AP7002 Reset Value – – – – – – – – – – 147 ...
Page 148
... The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end. 32054F–AVR32–09/ – – – – – – – – – – – – AT32AP7002 – – – – – – – – – ULBT 148 ...
Page 149
... This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE. 32054F–AVR32–09/ – – – FIXED_DEFMSTR – – – SLOT_CYCLE AT32AP7002 – – ARBT DEFMSTR_TYPE – – – 149 ...
Page 150
... Offset: - Reset Value: 0x00000000 31 30 M7PR 23 22 M5PR 15 14 M3PR 7 6 M1PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 32054F–AVR32–09/ AT32AP7002 M6PR M4PR M2PR M0PR 150 ...
Page 151
... Offset: - Reset Value: 0x00000000 31 30 M15PR 23 22 M13PR 15 14 M11PR 7 6 M9PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 32054F–AVR32–09/ AT32AP7002 M14PR M12PR M10PR M8PR 151 ...
Page 152
... Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master 32054F–AVR32–09/09 MRCR Read/Write – – – – – – RCB13 RCB12 RCB11 RCB5 RCB4 RCB3 AT32AP7002 – – – – – – RCB10 RCB9 RCB8 RCB2 RCB1 RCB0 152 ...
Page 153
... Access Type: Offset: 0x110 - 0x115 Reset Value • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used. 32054F–AVR32–09/09 SFR0...SFR15 Read/Write SFR SFR SFR SFR AT32AP7002 153 ...
Page 154
... Memory Controller. Data transfers are performed through a 16-bit data bus, an address bus bits three chip select lines (NCS[1:0] and NCS3) and several control pins that are generally multiplexed between the different external Memory Controllers. 32054F–AVR32–09/09 AT32AP7002 TM TM and CompactFlash Support ...
Page 155
... External Bus Interface 0 SDRAM Controller MUX Static Logic Memory Controller NAND Flash SmartMedia Logic ECC Controller Chip Select Assignor User Interface Peripheral Bus AT32AP7002 D[15:0] A0/NBS0 A1/NWR2/NBS2 A[15:2], A[22:18] A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS3/NANDCS NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS ...
Page 156
... SDA10 SDRAM Address 10 Line Depending on the Memory Controller in use, all signals are not connected directly through the Mux Logic. 32054F–AVR32–09/09 EBI SMC EBI for NAND Flash/SmartMedia Support SDRAM Controller AT32AP7002 Type Active Level I/O Output Output Low Output Low ...
Page 157
... EBI Pins and Memory Controllers I/O Lines Connections EBI Pins SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported SDRAMC_A[12:11] Not Supported Not Supported D[15:0] AT32AP7002 SMC I/O Lines NWR1/NUB SMC_A0/NLB SMC_A1 SMC_A[11:2] Not Supported SMC_A12 SMC_A[14:13] SMC_A[22:15] SMC_A[25:23] D[15:0] 157 ...
Page 158
... EBI pins and the EBI Pins and External Static Devices Connections 8-bit Static Device – A[2:22 – – 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2. AT32AP7002 Pins of the Interfaced Device 2 x 8-bit 16-bit Static Static Devices SMC D15 – A0 A[1:21 (1) WE ...
Page 159
... NANDOE NANDWE NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS CAS SDWE 32054F–AVR32–09/09 EBI Pins and External Devices Connections SDRAM SDRAMC AT32AP7002 Pins of the Interfaced Device Smart Media or NAND Flash SMC AD0-AD7 D8 - D15 AD8-AD15 DQM0 – DQM2 – A[0:8] – ...
Page 160
... EBI data bus and the CompactFlash slot. 2. Any PIO line. 3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For details, see ”SmartMedia and NAND Flash Support” on page AT32AP7002 Pins of the Interfaced Device Smart Media SDRAM or ...
Page 161
... CAS DQM NBS0 SDA10 A2-A15 A16/BA0 A17/BA1 A18-A22 NCS0 NCS1/SDCS NCS3 128K x 8 SRA M D0-D7 D0-D7 A0-A16 CS OE NRD/NOE WE A0/NWR0/NBS0 AT32AP7002 SDRA M D8-D15 D0-D7 CS CLK A2-A11, A13 A0-A9, A11 A2-A11, A13 CKE A10 SDA10 SDWE A10 SDA10 WE BA0 A16/BA0 BA0 A16/BA0 ...
Page 162
... For information on the Static Memory Controller, refer to the Static Memory Controller Section. 16.7.4 SDRAM Controller For information on the SDRAM Controller, refer to the SDRAM Section. 16.7.5 ECC Controller For information on the ECC Controller, refer to the ECC Section. 32054F–AVR32–09/09 AT32AP7002 162 ...
Page 163
... PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. 32054F–AVR32–09/09 SMC NCSx NRD_NOE NWR0_NWE AT32AP7002 for more informations. For details on these wave- SmartMedia Logic NANDOE NANDWE ”NAND Flash NANDOE ...
Page 164
... Figure 16-4. NAND Flash Application Example Note: 32054F–AVR32–09/09 D[7:0] A[22:21] NCSx/NANDCS EBI NANDOE NANDWE PIO PIO The External Bus Interfaces is also able to support 16-bits devices. AT32AP7002 AD[7:0] ALE CLE Not Connected SmartMedia NOE NWE CE R/B 164 ...
Page 165
... The master interface reads the data from a source and writes destination. Two System Bus transfers are required for each DMA data transfer. This is also known as a dual-access transfer. The DMACA is programmed via the HSB slave interface. 32054F–AVR32–09/09 AT32AP7002 165 ...
Page 166
... Peripherals Both the source peripheral and the destination peripheral must be set up correctly prior to the DMA transfer. 32054F–AVR32–09/09 HSB Slave HSB Slave I/F HSB Master HSB Master I/F AT32AP7002 DMA Controller Interrupt CFG Generator Channel 1 Channel 0 FIFO SRC DST FSM ...
Page 167
... In this mode, the peripheral is the flow controller. Flow control mode (CFGx.FCMODE): Special mode that only applies when the destination peripheral is the flow controller. It controls the pre-fetching of data from the source peripheral. 32054F–AVR32–09/09 AT32AP7002 167 ...
Page 168
... Burst Transfer Transfer DMAC Transfer Block Block System Bus System Bus Burst Burst Transfer Transfer AT32AP7002 illustrates the hierarchy between DMACA trans- shows the transfer hierarchy for memory. DMA Transfer Block Transfer Block Level DMA Transaction Single Level Transaction System Bus ...
Page 169
... HSB transfer from the source -(decoded value of CTLx.SRC_TR_WIDTH)/8 - when a gather boundary is reached. Gather is enabled by writing a ‘1’ to the CTLx.SRC_GATHER_EN bit. The CTLx.SINC field determines if the address is incremented, decremented or remains fixed when a gather bound- 32054F–AVR32–09/09 AT32AP7002 169 ...
Page 170
... A0 + 0x210 0x208 0x200 d10 d11 0 x 080 0x118 0x110 0x108 0x100 0 x 080 0x018 0x010 0x008 D0 A0 AT32AP7002 Scatter Boundary A0 + 0x220 Data Stream Scatter Boundary A0 + 0x120 Scatter Boundary A0 + 0x020 CTLx.DST_TR_WIDTH = 3'b011 (64bit bytes) DSR.DSI = 16 DSR.DSC = 4 DSR.DSI * 8 = 0x80 (Scatter Increment in bytes) 170 ...
Page 171
... A0 + 0x028 A0 + 0x020 0x01C 0x018 0x014 0x00C 0x008 0x004 D0 A0 AT32AP7002 Gather Boundary A0 + 0x38 Gather Increment = 4 Data Stream Gather Boundary A0 + 0x24 Gather Increment = 4 Gather Boundary A0 + 0x10 Gather Increment = 4 CTLx.SRC_TR_WIDTH = 3'b010 (32bit bytes) SGR.SGI = 1 SGR.SGC = 4 SGR.SGI * 4 = 0x4 (Gather Increment in bytes) 171 ...
Page 172
... System Bus. A non-memory peripheral can request a DMA transfer through the DMACA using one of two handshaking interfaces: • Hardware handshaking • Software handshaking 32054F–AVR32–09/09 shows the DMA transfer hierarchy of the DMACA for a memory periph- AT32AP7002 172 ...
Page 173
... There are 11 hardware handshaking interfaces between the DMACA and peripherals. Refer to the module configuration chapter for the device-specific mapping of these interfaces. 32054F–AVR32–09/09 The transaction-complete interrupts are triggered when both single and burst transactions are complete. The same transaction-complete interrupt is used for both single and burst transactions. AT32AP7002 173 ...
Page 174
... When block chaining, using linked lists is the multi-block method of choice, and on successive blocks, the LLPx register in the DMACA is re-programmed using the following method: • Block chaining using linked lists 32054F–AVR32–09/09 ”External DMA Request Timing” on page DMA Transaction DMA Transfers AT32AP7002 174). DMA Transfers 174 ...
Page 175
... CTLx with CTLx.LLP_S_EN and CTLx.LLP_D_EN. Figure 17-7. Multi-block Transfer Using Linked Lists CTLx[63..32] CTLx[31..0] LLPx(1) DARx SARx LLPx(0) 32054F–AVR32–09/09 shows how to use chained linked lists in memory to define multi-block System Memory LLI(0) CTLx[63..32] CTLx[31..0] LLPx(2) DARx SARx LLPx(1) AT32AP7002 LLI(1) LLPx(2) Fig- 175 ...
Page 176
... SARx, DARx and CTLx channel registers are AT32AP7002 CTLx, LLPx SARx DARx Update Update Update Method Method Method None, user None None (single) reprograms (single) CTLx,LLPx are Auto- reloaded from Contiguous Reload initial values. CTLx,LLPx are Con- ...
Page 177
... Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in Row 5 state enables status fetch for the last block. Ending in Row 1 state disables status fetch for the last block. Table 17-1 on page AT32AP7002 166). and setup the LLI.SARx address of the 176, the DMA transfer does not stall between block ...
Page 178
... Table 17-1 on page 176 is also a single block transfer. Program the LLPx register with ‘0’. For example, in the register, you can program the following: AT32AP7002 Table 17-1 on page 176 are from any row into 176. Table 17-1 on page 176 ...
Page 179
... Incrementing/decrementing or fixed address for destination in DINC field. Figure 17-7 on page tion) and flow control device by programming the TT_FC of the CTLx register. destination peripherals. This is not required for memory. This step requires program- AT32AP7002 175) for channel x. For example, in the 179 ...
Page 180
... The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automati- cally reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0). Table 17-1 on page 176 AT32AP7002 176. The LLI.CTLx register of the Table 17-1 on page Table 17-1 on page Table 17-1 on page 176 ...
Page 181
... CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as shown in Figure 17-9 on page 32054F–AVR32–09/09 Address of Source Layer Block 2 SAR(2) Block 1 SAR(1) Block 0 SAR(0) Source Blocks 182. AT32AP7002 Address of Destination Layer Block 2 DAR(2) Block 1 DAR(1) Block 0 DAR(0) Destination Blocks 181 ...
Page 182
... Address of Source Layer The DMA transfer flow is shown in 32054F–AVR32–09/09 Contiguous Block 2 SAR(3) Block 2 SAR(2) Block 1 SAR(1) Block 0 SAR(0) Source Blocks Figure 17-11 on page AT32AP7002 Address of Destination Layer Block 2 DAR(3) Block 2 DAR(2) Block 1 DAR(1) Block 0 DAR(0) Destination Blocks 185. 182 ...
Page 183
... Program the following channel registers: 32054F–AVR32–09/09 Channel enabled by software LLI Fetch Hardware reprograms SARx, DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Is DMAC in Row1 of no DMAC State Machine Table? yes Channel Disabled by hardware AT32AP7002 183 ...
Page 184
... It then stalls until the block complete interrupt is cleared by software. If the next block the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should AT32AP7002 Table 17-1 on page 176. If the DMACA is in Row 1, then the 176 ...
Page 185
... The transfer is similar to that shown in transfer flow is shown in Figure 17-12 on page Address of Source Layer SAR Source Blocks AT32AP7002 Table 17-1 on page 176. If the next before the last block of the DMA transfer has com- Figure 17-11 on page 186. Address of Destination Layer ...
Page 186
... Block Complete interrupt generated here DMAC transfer Complete interrupt generated here Channel Disabled by hardware tion) and flow control peripheral by programming the TT_FC of the CTLx register. AT32AP7002 Channel Enabled by software Block Transfer Reload SARx, DARx, CTLx yes Is DMAC in Row1 of DMAC State Machine Table? no CTLx ...
Page 187
... If the DMACA is in Row then the DMA transfer the following steps are performed. masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the AT32AP7002 while the LLI.CTLx register of the last Table 17-1 on page 176. ...
Page 188
... DMA transfer has completed. 176. The DMA transfer might look like that shown in Address of Source Layer SAR Source Blocks Destination Address Figure 17-14 on page AT32AP7002 176. Table 17-1 on page Table 17-1 on Figure 17-13 on page Address of Destination Layer Block0 ...
Page 189
... DMAC Transfer Complete interrupt generated here 32054F–AVR32–09/09 tion Address Source/destination status fetch Block Complete interrupt generated here yes Channel Disabled by hardware AT32AP7002 Channel Enabled by software LLI Fetch Hardware reprograms DARx, CTLx, LLPx DMAC block transfer Reload SARx Is DMAC in Row1 or Row5 of ...
Page 190
... Source master layer in the SMS field where source resides. – Destination master layer in the DMS field where destination resides. – Incrementing/decrementing or fixed address for source in SINC field. – Incrementing/decrementing or fixed address for destination in DINC field. AT32AP7002 Table 17-1 on page 176. Table 17-1 on page 176 ...
Page 191
... CFGx.RELOAD_SR, to put the device into ROW 1 of 176 before the last block of the DMA transfer has completed. Figure 17-15 on page Figure 17-16 on page nation Address Address of Source Layer SAR Source Blocks AT32AP7002 176. Table 17-1 on page 191. 192. Address of Destination Layer Block2 DAR(2) Block1 ...
Page 192
... Incrementing/decrementing or fixed address for source in SINC field. 32054F–AVR32–09/09 Address Block Complete interrupt generated here Channel Disabled by hardware tion) and flow control device by programming the TT_FC of the CTLx register. AT32AP7002 Channel Enabled by software Block Transfer Reload SARx, CTLx yes Is DMAC in Row1 of DMAC State Machine Table? no CTLx ...
Page 193
... LLI although fetched is not used. The DARx register in the DMACA remains unchanged. 176. The DMACA then knows that the previous block transferred was the AT32AP7002 176, while the LLI.CTLx register of the last Linked Table 17-1 on page Table 17-1 on page 176 ...
Page 194
... The DMA transfer flow is shown in Figure 17-18. 32054F–AVR32–09/09 Address Block 2 SAR(2) Block 1 SAR(1) Block 0 SAR(0) Source Blocks Figure 17-19 on page AT32AP7002 Figure 17-17 on page 194 Note that the des- Address of Destination Layer Block 2 DAR(2) Block 1 DAR(1) Block 0 DAR(0) Destination Blocks 195 ...
Page 195
... CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register (CFGx) register. 32054F–AVR32–09/09 Channel Enabled by software LLI Fetch Hardware reprograms SARx, CTLx, LLPx DMAC block transfer Source/destination status fetch generated here Is DMAC in Row 1 of Table 4 ? yes Channel Disabled by hardware AT32AP7002 no 195 ...
Page 196
... FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement. AT32AP7002 196 ...
Page 197
... Raw Status for IntErr Interrupt 0x2E8 Status for IntTfr Interrupt 0x2F0 Status for IntBlock Interrupt 0x2F8 Status for IntSrcTran Interrupt 32054F–AVR32–09/09 Register Register Name StatusSrcTran AT32AP7002 Access SAR0 Read/Write DAR0 Read/Write LLP0 Read/Write CTL0L Read/Write CTL0H Read/Write CFG0L ...
Page 198
... DMA Channel Enable Register 0x3F8 DMA Component ID Register Low 0x3FC DMA Component ID Register High 32054F–AVR32–09/09 Register Register Name StatusDstTran SglReqSrcReg SglReqDstReg DmaCompIdRegL DmaCompIdRegH AT32AP7002 Access Read-only StatusErr Read-only MaskTfr Read/Write MaskBlock Read/Write MaskSrcTran Read/Write MaskDstTran Read/Write MaskErr Read/Write ...
Page 199
... System Bus transfer. Updated after each source System Bus transfer. The SINC field in the CTLx register determines whether the address incre- ments, decrements left unchanged on every source System Bus transfer throughout the block transfer. 32054F–AVR32–09/ SADD[31:24 SADD[23:16 SADD[15: SADD[7:0] AT32AP7002 199 ...
Page 200
... System Bus transfer. Updated after each destination System Bus transfer. The DINC field in the CTLx register determines whether the address increments, decrements or is left unchanged on every destination System Bus transfer throughout the block transfer. 32054F–AVR32–09/ DADD[31:24 DADD[23:16 DADD[15: DADD[7:0] AT32AP7002 200 ...