AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 524

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

• DBW: Data Bus Width
• BAT: Byte Access Type
• EXNWMODE: External WAIT Mode
• WRITEMODE: Write Mode
32054F–AVR32–09/09
EXNWMODE
DBW
BAT
This field is used only if DBW defines a 16- or 32-bit data bus.
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the
read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for
the read and write controlling signal.
1: The write operation is controlled by the NWE signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setup of NCS.
0
1
2
3
0
1
2
3
0
1
External NWAIT Mode
Disabled:
the NWAIT input signal is ignored on the corresponding chip select.
Reserved
Frozen Mode:
if asserted, the NWAIT signal freezes the current read or write cycle. after deassertion, the read or write cycle
is resumed from the point where it was stopped.
Ready Mode:
the NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read
or write signal, to complete the access. If high, the access normally completes. If low, the access is extended
until NWAIT returns high.
Data Bus Width
8-bit bus
16-bit bus
32-bit bus
Reserved
Byte Access Type
Byte select access type:
Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2, and NBS3
Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2, and NBS3
Byte write access type:
Write operation is controlled using NCS, NWR0, NWR1, NWR2, and NWR3
Read operation is controlled using NCS and NRD
AT32AP7002
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