AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 538

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 28-9. Self Refresh Mode Behavior
28.7.6.2
32054F–AVR32–09/09
SDRAMC_A[12:0]
SDCKE
SDWE
SDCK
SDCS
RAS
CAS
Low power mode
and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR
register, and transmitted to the low power SDRAM device during initialization.
After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and
self refresh mode is activated, the SDRAMC issues an Extended Load Mode Register command
to the SDRAM and the Extended Mode Register of the SDRAM device is accessed automati-
cally. The PASR/DS/TCSR parameters values are therefore updated before entry into self
refresh mode.
The SDRAM device must remain in self refresh mode for a minimum period of t
remain in self refresh mode for an indefinite period. This is described in
538.
This mode is selected by writing the value two to the LPR.LPCB field. Power consumption is
greater than in self refresh mode. All the input and output buffers of the SDRAM device are
deactivated except SDCKE, which remains low. In contrast to self refresh mode, the SDRAM
device cannot remain in low power mode longer than the refresh period (64 ms for a whole
device refresh operation). As no auto refresh operations are performed by the SDRAM itself, the
SDRAMC carries out the refresh operation. The exit procedure is faster than in self refresh
mode.
This is described in
Figure 28-10 on page
Self Refresh Mode
539.
To the SDRAM Controller
Access Request
T
AT32AP7002
XSR
Figure 28-9 on page
= 3
RAS
Row
and may
538