AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 334

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

22.5
22.5.1
22.5.2
22.5.3
32054F–AVR32–09/09
CLOCK
DATA
Host Clock
Host Data
Device Clock
Device Data
Functional Description
Prescaler
Receiving data
Transmitting data
Figure 22-2. Host to device transfer
For all data transfers on the PS/2 bus, the device is responsible for generating the clock and
thus controlling the timing of the communications. When a host wants to initiate a transfer how-
ever, it needs to pull the clock line low for a given time (minimum 100µs). A clock prescaler
controls the timing of the transfer request pulse.
Before initiating host to device transfers, the programmer must write PSR (Prescale Register).
This value determines the length of the “transfer request” pulse and is found by:
According to the PS/2 specifications, the pulse length should be at least 100µs. The PS/2 mod-
ule frequency is the frequency of the peripheral bus to which the module is connected.
The receiver is enabled by writing the RXEN bit in CR (Control Register) to ‘1’. When enabled,
the receiver will continuously receive data transmitted by the device. The data is stored in RHR
(Receive Holding Register). When a byte has been received, the RXRDY bit in SR (Status Reg-
ister) is set.
For each received byte, the parity is calculated. If it doesn’t match the parity bit received from the
device, the PARITY bit in SR is set. The received byte should then be discarded.
If a received byte in RHR is not read before a new byte has been received, the overrun bit -
OVRUN in SR is set. The new data is stored in RHR overwriting the previously received byte.
The transmitter is enabled by writing the TXEN bit in CR to ‘1’. When enabled, a data transfer to
the device will be started by writing the transmit data to THR (Transmit Holding Register). Any
ongoing transfer from the device will be aborted.
PRSCV = Pulse length * PS/2 module frequency
AT32AP7002
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