AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 19

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

6.2.2
6.2.3
6.2.4
32054F–AVR32–09/09
AVR32B Microarchitecture Compliance
Java Support
Memory management
Figure 6-2.
.The follwing abbreviations are used in the figure:
AVR32 AP implements an AVR32B microarchitecture. The AVR32B microarchitecture is tar-
geted at applications where interrupt latency is important. The AVR32B therefore implements
dedicated registers to hold the status register and return address for interrupts, exceptions and
supervisor calls. This information does not need to be written to the stack, and latency is there-
fore reduced. Additionally, AVR32B allows hardware shadowing of the registers in the register
file.
The scall, rete and rets instructions use the dedicated return status registers and return address
registers in their operation. No stack accesses are performed by these instructions.
AVR32 AP provides Java hardware acceleration in the form of a Java Virtual Machine hardware
implementation. Refer to the AVR32 Java Technical Reference Manual for details.
AVR32 AP implements a full MMU as specified by the AVR32 architecture. The page sizes pro-
vided are 1K, 4K, 64K and 1M. A 32-entry fully-associative common TLB is implemented, as well
as a 4-entry micro-ITLB and 8-entry micro-DTLB. Instruction and data accesses perform lookups
in the micro-TLBs. If the access misses in the micro-TLBs, an access in the common TLB is per-
formed. If this access misses, a page miss exception is issued.
•IF1, IF2 - Instruction Fetch stage 1 and 2
•ID - Instruction Decode
•IS - Instruction Issue
•A1, A2 - ALU stage 1 and 2
•M1, M2 - Multiply stage 1 and 2
•DA - Data Address calculation stage
•D - Data cache access
•WB - Writeback
Prefetch unit
IF1
IF2
The AVR32 AP Pipeline
Decode unit
ID
IS
M1
DA
A1
M2
A2
D
AT32AP7002
WB
Multiply pipe
Load-store
ALU pipe
pipe
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