AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 317

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 21-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 21-6. Master Write with One Byte Internal Address and Multiple Data Bytes
Figure 21-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
32054F–AVR32–09/09
TXCOMP
TWD
TWD
TWD
TWD
TWD
TWD
TXRDY
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
S
S
S
S
Write THR
Write THR
DADR
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
other status bits, an interrupt can be generated if enabled in the interrupt enable register (IER).
After writing in the transmit-holding register (THR), setting the START bit in the control register
starts the transmission. The data is shifted in the internal shifter and when an acknowledge is
detected, the TXRDY bit is set until a new write in the THR (see
generates a stop condition to end the transfer.
The read sequence begins by setting the START bit. When the RXRDY bit is set in the status
register, a character has been received in the receive-holding register (RHR). The RXRDY bit is
reset when reading the RHR.
The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address).
The three internal address bytes are configurable through the Master Mode register (MMR). If
the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a slave address
higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave
address bits in the internal address register (IADR).
W
W
W
W
A
A
A
A
A
A
A
IADR(23:16)
IADR(15:8)
IADR(7:0)
IADR(7:0)
IADR(23:16)
IADR(15:8)
IADR(7:0)
A
A
A
A
A
A
A
IADR(15:8)
IADR(7:0)
S
DADR
DATA
IADR(15:8)
IADR(7:0)
DATA
R
A
A
Write THR
A
IADR(7:0)
S
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
DATA
A
S
R
Write THR
Figure 21-6
A
A
A
A
N
DADR
DATA
P
AT32AP7002
DATA
P
DATA
DATA
below). The master
R
N
A
A
P
N
A
P
P
P
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