AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 781

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

34.13.12 LCD Timing Configuration Register 1
Name: LCDTIM1
Access: Read/Write
Reset value: 0x0000000
• VFP: Vertical Front Porch
In TFT mode, these bits equal the number of idle lines at the end of the frame.
In STN mode, these bits should be set to 0.
• VBP: Vertical Back Porch
In TFT mode, these bits equal the number of idle lines at the beginning of the frame.
In STN mode, these bits should be set to 0.
• VPW: Vertical Synchronization pulse width
In TFT mode, these bits determine the vertical synchronization pulse width. VSYNC width is equal to (VPW+1) lines.
In STN mode, these bits should be set to 0.
• VHDLY: Vertical to horizontal delay
In TFT mode, this value determines the delay between VSYNC rising or falling edge and HSYNC rising edge. Delay is
(VHDLY+1) PCLK cycles.
In STN mode, these bits should be set to 0.
32054F–AVR32–09/09
31
23
15
7
-
-
30
22
14
6
-
-
29
21
13
5
-
28
20
12
4
-
VBP
VFP
27
19
11
3
VPW
26
18
10
2
VHDLY
AT32AP7002
25
17
9
1
24
16
8
0
781