AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 849

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Table 37-2.
37.6
37.6.1
37.6.2
37.6.3
32054F–AVR32–09/09
Instruction
OPCODE
Others
0x1F
0x12
0x13
0x17
Public JTAG instructions
IDCODE
SAMPLE_PRELOAD
INTEST
JTAG Instruction Summary
SYNC
N/A
Instruction
MEMORY_BLOCK_ACCESS
CANCEL_ACCESS
BYPASS
This instruction selects the 32 bit Device Identification register as Data Register. The Device
Identification register consists of a version number, a device number and the manufacturer code
chosen by JEDEC. This is the default instruction after power-up.
The active states are:
• Capture-DR: The static IDCODE value is latched into the shift register.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
JTAG instruction for taking a snap-shot of the input/output pins without affecting the system
operation, and pre-loading the scan chain without updating the DR-latch. The Boundary-Scan
Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.
• Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.
EXTEST
JTAG instruction for selecting the Boundary-Scan Chain as Data Register for testing circuitry
external to the AVR32 package. The contents of the latched outputs of the Boundary-Scan chain
is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.
The active states are:
• Capture-DR: Data on the external pins is sampled into the Boundary-Scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
This instruction selects the Boundary-Scan Chain as Data Register for testing internal logic in
the device. The logic inputs are determined by the Boundary-Scan Chain, and the logic outputs
are captured by the Boundary-Scan chain. The device output pins are driven from the Boundary-
Scan Chain.
Description
Select the SAB Data register as data register for the TAP. The
address is auto-incremented.
Cancel an ongoing Nexus or Memory access.
Synchronization counter
Bypass this device through the bypass register.
Acts as BYPASS
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