AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 528

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

28.5
28.5.1
Figure 28-2. SDRAM Controller Connections to SDRAM Devices: 32-bit Data Bus Width
32054F–AVR32–09/09
Application Example
Hardware Interface
SDRAMC_A[0-12]
Controller
SDRAM
DQM[0-3]
SDCKE
D0-D31
SDCS
SDWE
SDCK
RAS
CAS
BA0
BA1
Figure 28-2 on page 528
using a 32-bit data bus width.
connection using a 16-bit data bus width. It is important to note that these examples are given
for a direct connection of the devices to the SDRAMC, without External Bus Interface or I/O Con-
troller multiplexing.
D16-D23
D0-D7
DQM0
DQM2
D0-D7
D0-D7
CS
CLK
CS
CLK
CKE
WE
RAS
CAS
DQM
CKE
WE
RAS
CAS
DQM
SDRAM
SDRAM
2Mx8
2Mx8
A0-A9 A11
A0-A9 A11
A10
BA0
BA1
A10
BA0
BA1
shows an example of SDRAM device connection to the SDRAMC
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A10
BA1
SDRAMC_A10
BA1
BA0
BA0
Figure 28-3 on page 529
D24-D31
D8-D15
DQM1
DQM3
D0-D7
D0-D7
CS
CLK
CKE
RAS
CAS
CS
CLK
CKE
RAS
CAS
WE
DQM
WE
DQM
SDRAM
SDRAM
shows an example of SDRAM device
2Mx8
2Mx8
A0-A9 A11
A0-A9 A11
A10
BA0
BA1
A10
BA0
BA1
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A10
BA1
SDRAMC_A10
BA1
BA0
BA0
AT32AP7002
528