ZLP32300P2004G Zilog, ZLP32300P2004G Datasheet - Page 59

• Manufacturer Part Number: ZLP32300P2004G
• Description: IC CRIMZON Z8 MCU OTP 4K 20DIP
• Manufacturer: Zilog
• Series: Crimzon™ ZLPr

Specifications of ZLP32300P2004G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• For Use With: 269-4665 - KIT REMOTE UNVRSL USA 6-FUNCTION
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-3854

PS020823-0208
Watchdog Timer Mode
Watchdog Timer Mode Register (WDTMR)
The Watchdog Timer is a retriggerable one-shot timer that resets the Z8
terminal count. The WDT must initially be enabled by executing the WDT instruction. On
subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is
driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S),
and Overflow (V) Flags.
The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control
a tap circuit that determines the minimum time-out period. Bit 2 determines whether the
WDT is active during HALT, and Bit 3 determines WDT activity during Stop. Bits 4
through 7 are reserved (see
processor cycles (120 XTAL clocks) from the execution of the first instruction after
Power-on reset, Watchdog Reset, or a Stop Mode Recovery (see
point, the register cannot be modified by any means (intentional or otherwise). The
WDTMR cannot be read. The register is located in Bank F of the Expanded Register
Group at address location
WDTMR(0F)0Fh
D7
*Default setting after reset
Figure 35. Watchdog Timer Mode Register (Write Only)
D6
D5
D4
D3
0Fh
Figure
D2
. It is organized as shown in
D1
35). This register is accessible only during the first 60
D0
WDT TAP INT RC OSC
00
01*
10
11
WDT During HALT
0 OFF
1 ON *
WDT During Stop
0 OFF
1 ON *
Reserved (Must be 0)
Figure
20 ms min.
80 ms min.
10 ms min.
5 ms min.
Product Specification
Figure
35.
Crimzon
Functional Description
®
34). After this
if it reaches its
®
ZLP32300
55