EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 233

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
I
2
C Registers
If the AAK bit is cleared to 0 during a transfer, the I
on SDA) after the next byte is received, and sets the IFLG bit to 1. The I
contains the two status codes
general call address. The I
The section that follows describes each of the eZ80F91 ASSP’s Inter-Integrated Circuit
(I
Addressing
The CPU interface provides access to six 8-bit registers: four Read/Write registers, one
Read Only register and two Write Only registers, as indicated in
Table 123. I
Resetting the I
Hardware Reset—
I
I
Software Reset—
Register (I
register to 0 and sets the I
I
The I
allows 10-bit addressing in conjunction with the I
SLA[6:0] is the 7-bit address of the I
receives this address after a START condition, it enters SLAVE mode. I
sponds to the first bit received from the I
Register
I2C_SAR
I2C_XSAR
I2C_DR
I2C_CTL
I2C_SR
I2C_CCR
I2C_SRR
2
2
2
2
C Slave Address Register
C_SAR, I
C_SR register is set to
C) registers.
2
C_SAR register provides the 7-bit address of the I
2
2
C_SRR). A software reset clears the STP, STA, and IFLG bits of the I
C_XSAR, I2C_DR, and I
2
C Register Descriptions
Perform a software reset by writing any value to the I
2
When the I
C Registers
Description
Slave address register
Extended slave address register
Data byte register
Control register
Status register (Read Only)
Clock Control register (Write Only)
Software reset register (Write Only)
F8h
2
2
C back to an idle state.
C returns to an idle state when the IFLG bit is cleared to 0.
2
C is reset by a hardware reset of the eZ80F91 device, the
88h
.
or
2
98h
C when in 7-bit SLAVE mode. When the I
2
C_CTL registers are cleared to
2
if SLAVE RECEIVE mode is entered with the
C bus.
2
C_XSAR register. I
2
C transmits a NACK bit (High level
2
C when in SLAVE mode and
Product Specification
Table
I
2
2
2
00h
123.
C Serial I/O Interface
C Software Reset
C_SAR[7:1] =
2
2
eZ80F91 ASSP
C_SAR[7] corre-
C_SR register
; while the
2
2
C
C_CTL
225