C8051F326-GM Silicon Laboratories Inc, C8051F326-GM Datasheet
C8051F326-GM
Specifications of C8051F326-GM
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C8051F326-GM Summary of contents
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... Packages - 28-pin QFN - Temperature Range: –40 to +85 °C DIGITAL I/O UART Timer 0 VREG Timer 1 USB Controller / Transceiver LOW FREQUENCY OSCILLATOR HIGH-SPEED CONTROLLER CORE 8051 CPU (25MIPS) 8 DEBUG CIRCUITRY Copyright © 2008 by Silicon Laboratories C8051F326/7 Port 0 Port 2 Port 3 1536 B SRAM POR C8051F326/7 ...
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... C8051F326/7 2 Rev. 1.1 ...
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... Interrupt Priorities ..................................................................................... 49 6.3.4. Interrupt Latency ...................................................................................... 49 6.3.5. Interrupt Register Descriptions................................................................. 50 6.4. Power Management Modes .............................................................................. 55 6.4.1. Idle Mode.................................................................................................. 55 6.4.2. Stop Mode ................................................................................................ 55 7. Reset Sources ....................................................................................................... 57 7.1. Power-On Reset ............................................................................................... 58 7.2. Power-Fail Reset / VDD Monitor....................................................................... 59 7.3. External Reset .................................................................................................. 60 7.4. Missing Clock Detector Reset........................................................................... 60 C8051F326/7 Rev. 1.1 3 ...
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... External RAM ........................................................................................................ 69 9.1. Accessing User XRAM...................................................................................... 69 9.2. Accessing USB FIFO Space............................................................................. 70 10. Oscillators ............................................................................................................... 71 10.1.Programmable Internal Oscillator ..................................................................... 71 10.1.1.Adjusting the Internal Oscillator on C8051F326/7 Devices...................... 72 10.1.2.Internal Oscillator Suspend Mode ............................................................ 72 10.2.Internal Low-Frequency (L-F) Oscillator ........................................................... 74 10.3.CMOS External Clock Input.............................................................................. 74 10.4.4x Clock Multiplier ............................................................................................ 75 10.5.System and USB Clock Selection .................................................................... 76 10 ...
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... Timer .............................................................................. 128 14.1.2.Mode 1: 16-bit Timer .............................................................................. 129 14.1.3.Mode 2: 8-bit Timer with Auto-Reload.................................................... 129 14.1.4.Mode 3: Two 8-bit Timers (Timer 0 Only) .............................................. 130 15. C2 Interface ........................................................................................................... 135 15.1.C2 Interface Registers.................................................................................... 135 15.2.C2 Pin Sharing ............................................................................................... 137 Document Change List............................................................................................. 138 Contact Information.................................................................................................. 140 C8051F326/7 Rev. 1.1 5 ...
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... C8051F326/7 6 Rev. 1.1 ...
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... Figure 1.9. Development/In-System Debug Diagram............................................... 21 2. Absolute Maximum Ratings 3. Global DC Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. C8051F326 QFN-28 Pinout Diagram (Top View) .................................. 27 Figure 4.2. C8051F327 QFN-28 Pinout Diagram (Top View) .................................. 28 Figure 4.3. QFN-28 Package Drawing ..................................................................... 29 Figure 4.4. QFN-28 Recommended PCB Land Pattern ........................................... 30 5 ...
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... C8051F326/7 Figure 13.2. UART0 Timing Without Parity or Extra Bit.......................................... 120 Figure 13.3. UART0 Timing With Parity ................................................................. 120 Figure 13.4. UART0 Timing With Extra Bit ............................................................. 120 Figure 13.5. Typical UART Interconnect Diagram.................................................. 121 Figure 13.6. UART Multi-Processor Mode Interconnect Diagram .......................... 122 14. Timers Figure 14 ...
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... Table 10.2. Typical USB Low Speed Clock Settings ............................................... 76 Table 10.3. Internal Oscillator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 78 11. Port Input/Output Table 11.1. Port I/O DC Electrical Characteristics (C8051F326 Table 11.2. Port I/O DC Electrical Characteristics (C8051F327 12. Universal Serial Bus Controller (USB0) Table 12.1. Endpoint Addressing Scheme .............................................................. 88 Table 12 ...
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... C8051F326/7 10 Rev. 1.1 ...
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... USB Register Definition 12.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . . 97 USB Register Definition 12.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . . 99 USB Register Definition 12.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 100 USB Register Definition 12.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 100 USB Register Definition 12.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . . 101 C8051F326/7 Rev. 1.1 11 ...
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... C8051F326/7 USB Register Definition 12.12. OUT1INT: USB0 Out Endpoint Interrupt . . . . . . . . . . 101 USB Register Definition 12.13. CMINT: USB0 Common Interrupt . . . . . . . . . . . . . . . 102 USB Register Definition 12.14. IN1IE: USB0 IN Endpoint Interrupt Enable . . . . . . . . 102 USB Register Definition 12.15. OUT1IE: USB0 Out Endpoint Interrupt Enable . . . . . 103 USB Register Definition 12 ...
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... QFN packages with different pinouts. The RoHS compliant devices are marked with a -GM suffix in the part number. The port I/O on C8051F326 devices is powered from a separate I/O supply allowing it to interface to low voltage logic. Table 1.1. Product Selection Guide C8051F326-GM 25 16k C8051F327-GM ...
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... Brown- POR Out Low Freq Oscillator XTAL2 12 MHz Internal x4 2 Oscillator 1,2,3,4 2 USB Clock Clock XTAL2 Recovery D+ USB Transceiver D- VBUS Figure 1.1. C8051F326 Block Diagram 14 Port 0 Latch UART /SYSCLK Timer 0 FLASH 0 5 256 byte Reset SRAM Port 2 XRAM Latch SFR Bus ...
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... Figure 1.2. C8051F327 Block Diagram Port 0 Latch UART /SYSCLK Timer 0 FLASH 0 5 256 byte Reset SRAM Port 2 XRAM Latch SFR Bus System Clock e Port 3 Latch USB Rev. 1.1 C8051F326/7 P0.0/SYSCLK P P0.1 0 P0.2 P0.3/XTAL2 P0.4/TX D P0.5/RX r P0.6 v P0.7 P2.0 P P2.1 2 P2.2 P2.3 P2 P3.0/C2D ...
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... C8051F326/7 Figure 1.3. Typical Connections for the C8051F326 Figure 1.4. Typical Connections for the C8051F327 16 Rev. 1.1 ...
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... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F326/7 family utilizes Silicon Laboratories' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including two 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, 1536 bytes of on-chip RAM, 128 byte Special Function Register (SFR) address space, and 15 I/O pins ...
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... C8051F326/7 1.1.3. Additional Features The C8051F326/7 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 8 interrupt sources into the CIP-51. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The interrupt sources are very useful when building multi-tasking, real-time systems ...
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... Accessible through USB Registers Only Same 1024 bytes as from 0x0000 to 0x03FF, wrapped on 1K-byte boundaries 0x0400 0x03FF XRAM - 1024 Bytes (accessable using MOVX instruction) 0x0000 Rev. 1.1 C8051F326/7 Special Function Register's Lower 128 RAM (Direct and Indirect Addressing) USB FIFOs 256 Bytes 19 ...
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... D+ D- Figure 1.8. USB Controller Block Diagram 1.4. Voltage Regulator C8051F326/7 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software. 20 Serial Interface Engine (SIE) Endpoint0 IN/OUT ...
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... The C8051F326DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F326/7 MCUs. The kit includes a Windows development environment, a serial adapter for connecting to the C2 port, and a target application board. ...
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... C8051F326/7 devices include 15 I/O pins (one byte-wide Port, one 6-bit-wide and one 1-bit-wide Port). The C8051F326/7 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as a digital input or output pin. Pins selected as digital outputs may additionally be configured for push-pull or open-drain output. The “ ...
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... Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F326/7 Conditions Min Typ – ...
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... C8051F326/7 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 1,2 I/O Supply Voltage (VIO) 3 Core Supply Voltage (VDD) Core Supply Current with CPU VDD = 3.3 V, Clock = 24 MHz Active VDD = 3.3 V, Clock = 3 MHz VDD = 3 ...
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... Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F326/7 Pin Numbers Name ‘F326 ‘F327 VDD 6 6 VIO 5 — GND 2 3 RST C2CK P3. C2D REGIN 7 7 VBUS D– P0. XTAL2 P0 P0 Type Description Power 2.7–3.6 V Core Supply Voltage Input. ...
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... C8051F326/7 Table 4.1. Pin Definitions for the C8051F326/7 (Continued) Pin Numbers Name ‘F326 ‘F327 N.C. pins for the ‘F326: 13, 14, 15, 20, and 21. N.C. pins for the ‘F327: 13, 14, 15, 20, 21, and 22. 26 Type Description D I/O Port 0.6. See Section 11 for a complete description. ...
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... P0.0 1 GND C8051F326 D- 4 VIO 5 VDD 6 REGIN 7 Figure 4.1. C8051F326 QFN-28 Pinout Diagram (Top View) C8051F326/7 Top View GND Rev. 1.1 21 N.C. 20 N.C. 19 P2.0 18 P2.1 17 P2.4 16 P2.5 15 N.C. 27 ...
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... C8051F326/7 P0.1 1 P0.0 2 GND VDD 6 REGIN 7 Figure 4.2. C8051F327 QFN-28 Pinout Diagram (Top View) 28 C8051F327 Top View GND Rev. 1.1 21 N.C. 20 N.C. 19 P2.0 18 P2.1 17 P2.4 16 P2.5 15 N.C. ...
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... This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2 and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. C8051F326/7 Max Dimension Min 1. ...
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... C8051F326/7 Figure 4.4. QFN-28 Recommended PCB Land Pattern Table 4.3. QFN-28 PCB Land Pattern Dimensions Dimension Min C1 4.80 C2 4.80 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. ...
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... Voltage Regulator (REG0) C8051F326/7 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 5.1 for REG0 electrical characteristics. The voltage regulator is enabled on reset. When the device is self-powered from a 3V supply net, the reg- ulator may be disabled in order to save power ...
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... VDD Power Net 0.1 µF 1.0 µF Figure 5.2. REG0 Configuration: USB Self-Powered 32 C8051F326/7 VBUS Sense V In Voltage Regulator (REG0) V Out C8051F326/7 VBUS Sense V In Voltage Regulator (REG0) V Out Rev. 1.1 Device Power Net Device Power Net ...
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... From 5 V REGIN Power Net 0.1 µF 1.0 µ VDD Power Net 1.0 µF 0.1 µF Figure 5.4. REG0 Configuration: No USB Connection C8051F326/7 VBUS Sense V In Voltage Regulator (REG0) V Out VBUS Sense V In Voltage Regulator (REG0) V Out Rev. 1.1 Device Power Net ...
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... C8051F326/7 SFR Definition 5.1. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network). ...
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... DATA BUS B REGISTER TMP1 TMP2 SRAM ADDRESS ALU REGISTER DATA BUS BUFFER D8 SFR BUS D8 D8 INTERFACE D8 MEMORY MEM_WRITE_DATA A16 INTERFACE PIPELINE D8 INTERRUPT INTERFACE D8 D8 Rev. 1.1 C8051F326/7 STACK POINTER SRAM (256 X 8) SFR_ADDRESS SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA MEM_ADDRESS MEM_CONTROL MEM_READ_DATA SYSTEM_IRQs EMULATION_IRQ 35 ...
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... C8051F326/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
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... MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F326/7 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses external RAM (XRAM) and the on-chip program memory space implemented as re-programmable Flash memory. The Flash access feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section “ ...
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... C8051F326/7 Table 6.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte ...
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... CJNE Rn, #data, rel equal Compare immediate to indirect and jump if not CJNE @Ri, #data, rel equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation Program Branching Rev. 1.1 C8051F326/7 Clock Bytes Cycles ...
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... C8051F326/7 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (2s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00- 0x7F SFR (0x80-0xFF) ...
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... Byte Sectors) 0x0000 6.2.1. Program Memory The CIP-51 core has program memory space. The C8051F326/7 implements 16k kB of this pro- gram memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Addresses above 0x3DFF are reserved. Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL ...
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... C8051F326/7 6.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
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... Clock Control CLKMUL 0x91 Clock Multiplier CLKSEL 0xA9 Clock Select DPH 0x83 Data Pointer High DPL 0x82 Data Pointer Low EIE1 0xE6 Extended Interrupt Enable 1 C8051F326/7 OSCLCN OSCICL P0MDOUT SBRLL0 SBRLH0 TL1 TH0 TH1 DPH 3(B) 4(C) 5(D) Rev. 1.1 VDM0CN EIP1 ...
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... C8051F326/7 Table 6.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description EIE2 0xE7 Extended Interrupt Enable 2 EIP1 0xF6 Extended Interrupt Priority 1 EIP2 0xF7 Extended Interrupt Priority 2 EMI0CN 0xAA External Memory Interface Control ...
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... R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value 00000000 Bit0 SFR Address: 0x82 R/W Reset Value 00000000 Bit0 SFR Address: 0x83 R/W Reset Value 00000111 Bit0 SFR Address: ...
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... C8051F326/7 SFR Definition 6.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared to logic 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
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... Bit6 Bit5 Bits7– Register. This register serves as a second accumulator for certain arithmetic operations. R/W R/W R/W R/W B.4 B.3 B.2 B.1 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value B.0 00000000 Bit0 SFR Address: 0xF0 (bit addressable) 47 ...
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... C8051F326/7 6.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 8 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source, with the exception of USB0, has one or more associated interrupt-pending flag(s) located in an SFR. USB0 interrupt sources are located in the USB registers. See Section “ ...
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... The CPU is stalled during Flash write/erase operations. Interrupt service latency will be increased for inter- rupts occurring while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount of time the CPU is stalled. C8051F326/7 TMOD TMOD ...
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... C8051F326/7 Table 6.5. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 0x0003 (/INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (/INT1) Timer 1 Overflow 0x001B UART0 0x0023 USB0 0x0043 VBUS Level 0x007B *Note: See Section “12.8. Interrupts” on page 101 for more details about the USB interrupt. ...
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... This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. R/W R/W R/W R/W ES0 ET1 EX1 ET0 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value EX0 00000000 Bit0 SFR Address: 0xA8 (bit addressable) 51 ...
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... C8051F326/7 SFR Definition 6.8. IP: Interrupt Priority — — — Bit7 Bit6 Bit5 Bit7–5: Unused. Read = 100b. Write = don't care. Bit4: PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupts set to high priority level. ...
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... PUSB0 Bit4 Bit3 Bit2 Bit1 — — — — Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R Reset Value — 00000000 Bit0 SFR Address: 0xE6 R Reset Value — 00000000 Bit0 SFR Address: 0xF6 R/W Reset Value EVBUS 00000000 Bit0 SFR Address: ...
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... C8051F326/7 SFR Definition 6.12. EIP2: Extended Interrupt Priority — — — Bit7 Bit6 Bit5 Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: PVBUS: VBUS Level Interrupt Priority Control. This bit sets the priority of the VBUS interrupt. 0: VBUS interrupt set to low priority level. ...
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... If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU put to in STOP mode for longer than the MCD timeout of 100 µs. C8051F326/7 Rev. 1.1 55 ...
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... C8051F326/7 SFR Definition 6.13. PCON: Power Control R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7–2: GF5-GF0: General Purpose Flags 5-0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. ...
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... XTAL2 Clock Input Clock Select VDD Supply Monitor Enable + - Power On Reset Missing Clock Detector (one- shot) (Software Reset) EN SWRSF CIP-51 Microcontroller System Reset Core Extended Interrupt Handler Figure 7.1. Reset Sources Rev. 1.1 C8051F326/7 '0' /RST (wired-OR) Reset Funnel Errant FLASH Operation 57 ...
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... C8051F326/7 7.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above Power-On Reset delay (T RST PORDelay typically less than 0.3 ms. Figure 7.2. plots the power-on and VDD monitor reset timing. ...
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... This bit indicates the current power supply status (VDD Monitor output). 0: VDD below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. Bits5–0: Reserved. Read = Variable. Write = don’t care Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 , the power supply RST R Reset Value Variable Bit0 SFR Address: 0xFF 59 ...
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... C8051F326/7 7.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 7.1 for complete RST pin spec- ifications ...
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... Source of last reset was not RST pin. 1: Source of last reset was RST pin. Note: Do not use read-modify-write instructions on this register. R/W R R/W R/W — MCDRSF PORSF Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R Reset Value PINRSF Variable Bit0 SFR Address: 0xEF 61 ...
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... C8051F326/7 Table 7.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter ‘F326 RST Output Voltage ‘F327 RST Output Voltage I OL RST Input High Voltage* RST Input Low Voltage* ‘F326 RST Pullup Current ‘F327 RST Pullup Current VDD Monitor Threshold (V ...
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... Step 4. Set the PSEE bit (register PSCTL). Step 5. Set the PSWE bit (register PSCTL). Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE bit (register PSCTL). Step 8. Clear the PSEE bit (register PSCTI). C8051F326/7 Rev. 1.1 63 ...
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... Steps 3-8 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be cleared so that MOVX instructions do not target program memory. Table 8.1. Flash Electrical Characteristics Parameter Flash Size C8051F326/7 Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock *Note: 512 bytes at location 0x3E00 to 0x3FFF are reserved ...
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... Lock Byte. 6. Locked pages can only be unlocked through the C2 interface with a C2 Device Erase com- mand user firmware Flash access attempt is denied (per restrictions #3, #4, and #5 above), a Flash Error system reset will be generated. C8051F326/7 Rev. 1.1 65 ...
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... Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction. The Flash location should be erased before writing data. 0: Writes to Flash program memory disabled. 1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash memory. 66 C8051F326/7 Reserved 0x3E00 Lock Byte 0x3DFF 0x3DFE ...
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... Flash one-shot enabled. Bits6–0: Reserved. Read = 0. Must Write 0. R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value 00000000 Bit0 SFR Address: 0xB7 R/W Reset Value Bit0 SFR Address: 0xB6 67 ...
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... C8051F326/7 68 Rev. 1.1 ...
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... External RAM The C8051F326/7 devices include 1280 bytes of on-chip XRAM. This XRAM space is split into user RAM (addresses 0x0000–0x03FF) and USB0 FIFO space. The USB0 FIFO space is only accessible through the USB FIFO registers fro rie Figure 9.1. External Ram Memory Map 9 ...
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... C8051F326/7 9.2. Accessing USB FIFO Space The upper 256 bytes of XRAM functions as USB FIFO space. Figure 9.2 shows an expanded view of the FIFO space and user XRAM. FIFO space is accessed via USB FIFO registers; see Section “12.5. FIFO Management” on page 95 for more information on accessing these FIFOs. The FIFO block operates on the USB clock domain ...
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... Programmable Internal Oscillator All C8051F326/7 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register. On C8051F326/7 devices, OSCICL is factory calibrated to obtain a 12 MHz frequency. Electrical specifications for the preci- sion internal oscillator are given in Table 10 ...
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... C8051F326/7 10.1.1. Adjusting the Internal Oscillator on C8051F326/7 Devices The OSCICL reset value is factory calibrated to result MHz internal oscillator with a ±1.5% accu- racy; this frequency is suitable for use as the USB clock (see Section “10.5. System and USB Clock Selec- tion” on page 76). Software may adjust the frequency of the internal oscillator using the OSCICL register. ...
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... Note: The contents of this register are undefined when Clock Recovery is enabled. See Section “12.4. USB Clock Configuration” on page 94 for details on Clock Recovery. R/W R/W R/W R/W OSCCAL Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value Variable Bit0 SFR Address: 0xB3 73 ...
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... C8051F326/7 10.2. Internal Low-Frequency (L-F) Oscillator C8051F326/7 devices include a low-frequency oscillator. The OSCLCN register (see SFR Definition 10.3) is used to enabled the oscillator. SFR Definition 10.3. OSCLCN: Internal L-F Oscillator Control R OSCLEN — — Bit7 Bit6 Bit5 Bit7: OSCLEN: Internal L-F Oscillator Enable. ...
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... This bit selects the clock supplied to the Clock Multiplier. MULSEL 0 1 R/W R/W R/W R/W — — — — Bit4 Bit3 Bit2 Bit1 Selected Clock Internal Oscillator External Clock Rev. 1.1 C8051F326/7 R/W Reset Value MULSEL 00000000 Bit0 SFR Address 0xB9 75 ...
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... C8051F326/7 10.5. System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immedi- ately following the OSCICN write that enables the internal oscillator. If the external clock is selected as the system or USB clock, then startup times may vary based on the specifications of the external clock. ...
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... Bit1 Selected Clock 4x Clock Multiplier Internal Oscillator / 2 External Oscillator Clock Off (0 Hz) Selected Clock Internal Oscillator (as determined by the IFCN bits in register OSCICN) External Clock 4x Clock Multiplier / 2 Low Frequency Oscillator RESERVED Rev. 1.1 C8051F326/7 R/W Reset Value 00000000 Bit0 SFR Address 0xA9 77 ...
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... C8051F326/7 Table 10.3. Internal Oscillator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Internal High-Frequency Oscillator Internal Oscillator Frequency Reset Frequency Internal Oscillator Supply OSCICN Current (from VDD) 1 USB Clock Frequency Full Speed Mode Low Speed Mode Internal Low-Frequency Oscillator (Using Factory-Calibrated Settings) ...
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... I/O Cell (P0.0 - IN) TMOD.3 I/O Cell TMOD.3 I/O Cell I/O Cell (P0.4 - IN) I/O (P0.4 - OUT) Cell (P0.5 - IN) I/O (P0.5 - OUT) Cell 2 I/O Cells 6 I/O Cells I/O Cell Rev. 1.1 C8051F326/7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.5 P3.0 79 ...
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... C8051F326/7 /WEAK-PULLUP PUSH-PULL Logic 0 PORT-OUTPUT INPUTEN PORT-INPUT Figure 11.2. Port I/O Cell Block Diagram 80 Supply Supply (WEAK) GND Rev. 1.1 PORT PAD ...
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... JBC, CPL, INC, DEC, and DJNZ. The MOV, CLR and SETB instructions are also read-modify-write when the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR. C8051F326/7 Rev. 1.1 81 ...
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... C8051F326/7 SFR Definition 11.1. GPIOCN: Global Port I/O Control R/W R/W R WEAKPUD INPUTEN — Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for I/O pins with Port latches set to logic 0 or are config- ured to push-pull mode). ...
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... Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W — — — — Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value P2.0 11111111 Bit0 SFR Address: 0xA0 (bit addressable) R/W Reset Value 00000000 Bit0 SFR Address: 0xA6 R/W Reset Value P3 ...
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... C8051F326/7 SFR Definition 11.7. P3MDOUT: Port3 Output Mode R/W R/W R/W — — — Bit7 Bit6 Bit5 Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: Output Configuration Bit for P3.0: 0: P3.0 Output is open-drain. 1: P3.0 Output is push-pull. 84 R/W R/W R/W R/W — ...
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... Table 11.1. Port I/O DC Electrical Characteristics (C8051F326) VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified Parameter Output High Voltage IOH = –10 µA; Port I/O push-pull IOH = –3 mA; Port I/O push-pull IOH = –10 mA; Port I/O push-pull Output Low Voltage µA OL IOL = 8.5 mA ...
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... C8051F326 OTES 86 Rev. 1.1 ...
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... Universal Serial Bus Controller (USB0) C8051F326/7 devices include a complete Full/Low Speed USB function for USB peripheral implementa- tions*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pullup resistors), 256 Byte FIFO block, and clock recovery mechanism for crystal-less operation ...
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... C8051F326/7 12.1. Endpoint Addressing A total of three endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. Endpoint 1 is implemented byte IN pipe and a 128 byte OUT pipe: Table 12.1. Endpoint Addressing Scheme Endpoint Associated Pipes Endpoint0 Endpoint1 12.2. USB Transceiver The USB Transceiver is configured via the USB0XCN register shown in Figure 12 ...
Page 89
... D+ signal currently at logic signal currently at logic 1. Bit0: Dn: D- Signal Status This bit indicates the current logic level of the D- pin signal currently at logic signal currently at logic 1. R/W R Bit4 Bit3 Bit2 Bit1 Mode Rev. 1.1 C8051F326/7 R Reset Value Dn 00000000 Bit0 SFR Address: 0xD7 D– ...
Page 90
... C8051F326/7 12.3. USB Register Access The USB0 controller registers listed in Table 12.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 12.2. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end- point number. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the “ ...
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... USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the register indicated by the USBADDR bits. R/W R/W R/W R/W USBADDR Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value 00000000 Bit0 SFR Address: 0x96 91 ...
Page 92
... C8051F326/7 USB Register Definition 12.3. USB0DAT: USB0 Data R/W R/W R/W Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. ...
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... Endpoint IN Control / Status High Byte Endpoint OUT Control / Status Low Byte Endpoint OUT Control / Status High Byte Number of Received Bytes in Endpoint0 FIFO Endpoint OUT Packet Count Low Byte Endpoint OUT Packet Count High Byte Rev. 1.1 C8051F326/7 Page Number 101 101 102 102 103 ...
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... C8051F326/7 12.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “ ...
Page 95
... Table 12.3. FIFO Configurations Endpoint Split Mode Number Enabled Endpoint0 (IN/OUT) Control Endpoint Endpoint1 (Split IN/OUT) USB Clock Domain System Clock Domain Maximum IN Packet Size Maximum OUT Packet (Double Buffer Disabled / Size (Double Buffer Dis- Enabled) abled / Enabled Rev. 1.1 C8051F326/7 128 / 64 95 ...
Page 96
... C8051F326/7 12.5.1. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end- point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO ...
Page 97
... Holds the 7-bit function address for USB0. This address should be written by software when the SET_ADDRESS standard device request is received on Endpoint0. The new address takes effect when the device request completes. R/W R/W R/W R/W Function Address Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value 00000000 Bit0 USB Address: 0x00 97 ...
Page 98
... C8051F326/7 12.7. Function Configuration and Control The USB register POWER (Figure 12.8) is used to configure and control USB0 at the device level (enable/ disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to ‘1’ by hardware when Reset signaling is detected on the bus. Upon this detection, the following occur: 1 ...
Page 99
... Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. R/W R/W R/W R USBRST RESUME SUSMD Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value SUSEN 00010000 Bit0 USB Address: 0x01 99 ...
Page 100
... C8051F326/7 USB Register Definition 12.9. FRAMEL: USB0 Frame Number Low Bit7 Bit6 Bit5 Bits7–0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 12.10. FRAMEH: USB0 Frame Number High — — — Bit7 Bit6 Bit5 Bits7– ...
Page 101
... Unused. Read = 0. Write = don’t care — — — IN1 Bit4 Bit3 Bit2 Bit1 — — — OUT1 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R Reset Value EP0 00000000 Bit0 USB Address: 0x02 R Reset Value — 00000000 Bit0 USB Address: 0x04 101 ...
Page 102
... C8051F326/7 USB Register Definition 12.13. CMINT: USB0 Common Interrupt — — — Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token is received. This interrupt event is synthesized by hard- ware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted ...
Page 103
... OUT1E Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W — SOFE RSTINTE RSUINTE SUSINTE 00000110 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value — 00000010 Bit0 USB Address: 0x09 R/W Reset Value Bit0 USB Address: 0x0B 103 ...
Page 104
... C8051F326/7 12.9. The Serial Interface Engine The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automat- ically generated by the SIE ...
Page 105
... Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the STALL is transmitted. C8051F326/7 Rev. 1.1 105 ...
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... C8051F326/7 USB Register Definition 12.17. E0CSR: USB0 Endpoint0 Control R/W R/W R/W SSUEND SOPRDY SDSTL Bit7 Bit6 Bit5 Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND. ...
Page 107
... Bits6–0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a ‘1’ E0CNT Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R Reset Value 00000000 Bit0 USB Address: 0x16 107 ...
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... C8051F326/7 12.11. Configuring Endpoint1 Endpoint1 is configured and controlled through a set of control/status registers: IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. The endpoint control/status registers are mapped into the USB register address space based on the contents of the INDEX register (Figure 12.4). ...
Page 109
... FIFO. The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame; the packet will only be sent after a SOF signal has been received. C8051F326/7 Rev. 1.1 109 ...
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... C8051F326/7 USB Register Definition 12.19. EINCSRL: USB0 IN Endpoint Control Low Byte R W R/W — CLRDT STSTL Bit7 Bit6 Bit5 Bit7: Unused. Read = 0. Write = don’t care. Bit6: CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’. ...
Page 111
... Endpoint data toggle forced to switch after every data packet is transmitted, regardless of ACK reception. Bits2-0: Unused. Read = 000b. Write = don’t care — FCDT — — Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R Reset Value — 00000000 Bit0 USB Address: 0x12 111 ...
Page 112
... C8051F326/7 12.13. Controlling Endpoint1 OUT Endpoint1 OUT is managed via USB registers EOUTCSRL and EOUTCSRH. It can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware. ...
Page 113
... Hardware sets this bit to ‘1’ and generates an interrupt when a data packet is available. Soft- ware should clear this bit after each data packet is unloaded from the OUT endpoint FIFO. R/W R R/W FLUSH DATERR OVRUN FIFOFUL Bit4 Bit3 Bit2 Rev. 1.1 C8051F326/7 R R/W Reset Value OPRDY 00000000 Bit1 Bit0 USB Address: 0x14 113 ...
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... C8051F326/7 USB Register Definition 12.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte R/W R/W R/W DBOEN ISO — Bit7 Bit6 Bit5 Bit7: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. Bit6: ISO: Isochronous Transfer Enable This bit enables/disables isochronous transfers on the current endpoint ...
Page 115
... Full Speed (D+ Pullup) 1.425 Low Speed (D– Pullup) — Low Speed 75 Full Speed 4 Low Speed 75 Full Speed 4 | (D+) – (D–) | 0.2 0.8 Pullups Disabled — Rev. 1.1 C8051F326/7 Typ Max Units 5.7 — mA 1.5 — — V — 0.8 V — 2 — ...
Page 116
... C8051F326/7 116 Rev. 1.1 ...
Page 117
... Baud Rate Generator SBRLH0 SBRLL0 Overflow SYSCLK Timer (16-bit) USBCLK EN SBCON0 Figure 13.1. UART0 Block Diagram Data Formatting SMOD0 Pre-Scaler (1, 4, 12, 48) Control / Status SCON0 UART0 Interrupt Rev. 1.1 C8051F326/7 TX TX0 Logic Write to SBUF0 SBUF0 Read of SBUF0 RX FIFO (3 Deep) RX RX0 Logic 117 ...
Page 118
... C8051F326/7 13.1. Baud Rate Generator The UART0 baud rate is generated by a dedicated 16-bit timer which runs from either the controller’s core clock (SYSCLK) or the USB Clock (USBCLK), and has prescaler options 12, or 48. The timer and prescaler options combined allow for a wide selection of baud rates over many clock frequencies. ...
Page 119
... C8051F326/7 Oscillator SB1PS[1:0] Divide (Prescaler Bits) Factor 52 11 104 11 208 11 416 11 834 11 1250 11 5000 11 10000 11 104 11 208 ...
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... C8051F326/7 13.2. Data Format UART0 has a number of available options for data formatting. Data transfers begin with a start bit (logic low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity ...
Page 121
... If the extra bit function is enabled (XBE0 = ‘1’) and the parity function is disabled (PE0 = ‘0’), the extra bit for the oldest byte in the FIFO can be read from the RBX0 bit (SCON0.2). If the extra bit function is not TX RS-232 RS-232 C8051Fxxx LEVEL RX TRANSLATOR MCU C8051Fxxx RX RX Rev. 1.1 C8051F326/7 121 ...
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... C8051F326/7 enabled, the value of the stop bit for the oldest FIFO byte will be presented in RBX0. When the parity func- tion is enabled (PE0 = ‘1’), hardware will check the received parity bit against the selected parity type (selected with S0PT[1:0]) when receiving data byte with parity error is received, the PERR0 flag will be set to ‘ ...
Page 123
... When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by soft- ware. R/W R/W R/W R/W REN0 TBX0 RBX0 TI0 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value RI0 00100000 Bit Bit0 Addressable 0x98 SFR Address: 123 ...
Page 124
... C8051F326/7 SFR Definition 13.2. SMOD0: UART0 Mode R/W R/W R/W MCE0 S0PT1 S0PT0 Bit7 Bit6 Bit5 Bit7: MCE0: Multiprocessor Communication Enable will be activated if stop bit(s) are ‘1’ will be activated if stop bit(s) and extra bit are ‘1’ (extra bit must be enabled using XBE0) ...
Page 125
... Prescaler = 48 11: Prescaler = 1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value 00000000 Bit0 0x99 SFR Address: R/W Reset Value SB0PS0 00000000 Bit Bit0 Addressable 0x91 SFR Address: 125 ...
Page 126
... C8051F326/7 SFR Definition 13.5. SBRLH0: UART0 Baud Rate Generator High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SBRLH0[7:0]: High Byte of reload value for UART0 Baud Rate Generator. SFR Definition 13.6. SBRLL0: UART0 Baud Rate Generator Low Byte R/W R/W R/W ...
Page 127
... IE register (SFR Definition 6.7). Both timers operate in one of four primary modes selected by set- ting the Mode Select bits T1M1-T0M0 in the Timer Mode register (TMOD). Each timer can be configured independently. Each operating mode is described below. Table 14.1. Timer Modes Timer 0 and Timer 1 Modes: Rev. 1.1 C8051F326/7 127 ...
Page 128
... C8051F326/7 14.1.1. Mode 0: 13-bit Timer Timer 0 and Timer 1 operate as 13-bit timers in Mode 0. The following describes the configuration and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same man- ner as described for Timer 0. The TH0 register holds the eight MSBs of the 13-bit timer. TL0 holds the five LSBs in bit positions TL0.4- TL0 ...
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... Section “6.3.2. External Interrupts” on page 49 for details on the external input sig- nals /INT0 and /INT1). CKCON Pre-scaled Clock SYSCLK TMOD GATE0 /INT0 Figure 14.2. T0 Mode 2 Block Diagram TCLK TL0 TR0 (8 bits) TH0 (8 bits) Rev. 1.1 C8051F326/7 TF1 TR1 TF0 Interrupt TR0 IE1 IT1 IE0 IT0 Reload 129 ...
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... C8051F326/7 14.1.4. Mode 3: Two 8-bit Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit timers held in TL0 and TH0. The counter in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 131
... This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. 0: /INT0 is level triggered. 1: /INT0 is edge triggered. R/W R/W R/W R/W TR0 IE1 IT1 IE0 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F326/7 R/W Reset Value IT0 00001010 Bit0 SFR Address: 0x88 (bit addressable) 131 ...
Page 132
... C8051F326/7 SFR Definition 14.2. TMOD: Timer Mode R/W R/W R/W GATE1 Reserved T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. /INT1 is activated when the internal oscillator resumes from a suspended state. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active. /INT1 is activated every 2 low frequency oscillator clock cycles ...
Page 133
... Note: External clock divided synchronized with the system clock. R/W R/W R/W R/W — T1M T0M SCA1 Bit4 Bit3 Bit2 Bit1 Prescaled Clock System clock divided by 12 System clock divided by 4 System clock divided by 48 Rev. 1.1 C8051F326/7 R/W Reset Value SCA0 00000000 Bit0 SFR Address: 0x8E 133 ...
Page 134
... C8051F326/7 SFR Definition 14.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 14.5. TL1: Timer 1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7– ...
Page 135
... C2 Interface C8051F326/7 devices include an on-chip Silicon Laboratories 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2 protocol. ...
Page 136
... C8051F326/7 C2 Register Definition 15.3. REVID: C2 Revision ID Bit7 Bit6 Bit5 This read-only register returns the 8-bit revision ID: 0x01 (Revision B). C2 Register Definition 15.4. FPCTL: C2 Flash Programming Control Bit7 Bit6 Bit5 Bits7–0 FPCTL: Flash Programming Control Register. This register is used to enable Flash programming via the C2 interface. To enable C2 Flash programming, the following codes must be written in order: 0x02, 0x01 ...
Page 137
... The configuration in Figure 15.1 assumes the following: 1. The user input (b) cannot change state while the target device is halted. 2. The /RST pin on the target device is used as an input only. Additional resistors may be necessary depending on the specific application. C8051F326/7 C2CK C2D C2 Interface Master Rev. 1.1 C8051F326/7 137 ...
Page 138
... Changed “-GQ” references to “-GM” • Added Figure 1.3. "Typical Connections for the C8051F326" on page 16 and Figure 1.4. "Typical Con- nections for the C8051F327" on page 16. • Changed Figure 4.5. "Typical C8051F327 QFN-28 Landing Diagram" on page 31 to show ground con- nection on Pin 3. • ...
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... N : OTES C8051F326/7 Rev. 1.1 139 ...
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... C8051F326 ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: MCUinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice ...