C8051F541-IQ Silicon Laboratories Inc, C8051F541-IQ Datasheet - Page 147

• Manufacturer Part Number: C8051F541-IQ
• Description: IC 8051 MCU 16K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F54xr

Specifications of C8051F541-IQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 32-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F540DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1674

18. Port Input/Output
Digital and analog resources are available through 25 (C8051F540/1/4/5) or 18 (C8051F542/3/6/7) I/O
pins. Port pins P0.0-P3.0 on the C8051F540/1/4/5 and port pins P0.0-P2.1 on the C8051F542/3/6/7 can
be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to
an analog function as shown in Figure 18.3. Port pin P3.0 on the C8051F540/1/4/5 can be used as GPIO
and is shared with the C2 Interface Data signal (C2D). Similarly, port pin P2.1 is shared with C2D on the
C8051F542/3/6/7. The designer has complete control over which functions are assigned, limited only by
the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Prior-
ity Crossbar Decoder. The state of a Port I/O pin can always be read in the corresponding Port latch,
regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 18.3 and Figure 18.4). The registers XBR0, XBR1, XBR2 are defined in SFR Definition 18.1 and
SFR Definition 18.2 and are used to select internal digital functions.
The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers
(PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Table 6.3 on
page 51.
Lowest
Priority
Highest
Priority
Latches
Port
/SYSCLK
SMBus0
UART0
T0, T1,
/INT0,
PCA0
/INT1
SPI0
LIN0
CP0
CP1
P0
P1
P2
P3
(Px.0-Px.7)
25
Figure 18.1. Port I/O Functional Block Diagram
2
4
2
2
2
7
4
2
XBR2, PnSKIP
XBR0, XBR1,
Crossbar
Decoder
Priority
Rev. 1.1
Digital
8
8
8
8
PnDMIN Registers
PnMDOUT,
Cells
Cells
Cells
Cell
P0
I/O
P1
I/O
P2
I/O
P3
I/O
PnMATCH
Registers
PnMASK
C8051F54x
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
Highest
Priority
Lowest
Priority
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