C8051F561-IQ Silicon Laboratories Inc, C8051F561-IQ Datasheet - Page 258

• Manufacturer Part Number: C8051F561-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F561-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1696

C8051F55x/56x/57x
25.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “13.3. External Interrupts INT0 and INT1”
on page 122 for details on the external input signals INT0 and INT1).
258
/IN T 0
T 0
C ro s s b a r
P re -s c a le d C lo c k
S Y S C L K
IN 0 P L
G A T E 0
X O R
Figure 25.1. T0 Mode 0 Block Diagram
T R 0
0
1
M
H
T
3
M
T
3
L
C K C O N
M
H
T
2
T
M
2
L
0
1
M
T
1
M
T
0
C
S
A
1
S
C
A
0
Rev. 1.1
G
A
T
E
1
C
T
1
/
M
T
1
1
T M O D
M
T
1
0
T C L K
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 b its )
T L 0
N
P
1
L
I
N
1
S
L
2
I
IT 0 1 C F
N
S
1
L
1
I
N
S
1
L
0
I
N
0
P
L
I
(8 b its )
T H 0
N
S
0
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
T R 1
T R 0
T F 1
T F 0
IE 1
IE 0
IT 1
IT 0
In te rru p t