C8051F561-IQ Silicon Laboratories Inc, C8051F561-IQ Datasheet - Page 6

IC 8051 MCU 32K FLASH 32-QFP

C8051F561-IQ

Manufacturer Part Number
C8051F561-IQ
Description
IC 8051 MCU 32K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Datasheets

Specifications of C8051F561-IQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1696

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F561-IQ
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
C8051F561-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F561-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F55x/56x/57x
22. SMBus................................................................................................................... 216
23. UART0 ................................................................................................................... 233
24. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 242
25. Timers ................................................................................................................... 255
6
22.1. Supporting Documents .................................................................................. 217
22.2. SMBus Configuration..................................................................................... 217
22.3. SMBus Operation .......................................................................................... 217
22.4. Using the SMBus........................................................................................... 219
22.5. SMBus Transfer Modes................................................................................. 226
22.6. SMBus Status Decoding................................................................................ 230
23.1. Baud Rate Generator .................................................................................... 233
23.2. Data Format................................................................................................... 235
23.3. Configuration and Operation ......................................................................... 236
24.1. Signal Descriptions........................................................................................ 243
24.2. SPI0 Master Mode Operation ........................................................................ 244
24.3. SPI0 Slave Mode Operation .......................................................................... 246
24.4. SPI0 Interrupt Sources .................................................................................. 246
24.5. Serial Clock Phase and Polarity .................................................................... 247
24.6. SPI Special Function Registers ..................................................................... 248
25.1. Timer 0 and Timer 1 ...................................................................................... 257
21.2.2. Message Object Interface Registers ..................................................... 212
21.2.3. Message Handler Registers.................................................................. 212
21.2.4. CAN Register Assignment .................................................................... 213
22.3.1. Transmitter Vs. Receiver....................................................................... 218
22.3.2. Arbitration.............................................................................................. 218
22.3.3. Clock Low Extension............................................................................. 218
22.3.4. SCL Low Timeout.................................................................................. 218
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 219
22.4.1. SMBus Configuration Register.............................................................. 219
22.4.2. SMB0CN Control Register .................................................................... 223
22.4.3. Data Register ........................................................................................ 226
22.5.1. Write Sequence (Master) ...................................................................... 227
22.5.2. Read Sequence (Master) ...................................................................... 228
22.5.3. Write Sequence (Slave) ........................................................................ 229
22.5.4. Read Sequence (Slave) ........................................................................ 230
23.3.1. Data Transmission ................................................................................ 236
23.3.2. Data Reception ..................................................................................... 236
23.3.3. Multiprocessor Communications ........................................................... 237
24.1.1. Master Out, Slave In (MOSI)................................................................. 243
24.1.2. Master In, Slave Out (MISO)................................................................. 243
24.1.3. Serial Clock (SCK) ................................................................................ 243
24.1.4. Slave Select (NSS) ............................................................................... 243
25.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 257
25.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 258
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 258
Rev. 1.1

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