C8051F411-GM Silicon Laboratories Inc, C8051F411-GM Datasheet - Page 155

• Manufacturer Part Number: C8051F411-GM
• Description: IC 8051 MCU 32K FLASH 28QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F41xr

Specifications of C8051F411-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 20
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 20x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2368 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• No. Of I/o's: 20
• Ram Memory Size: 2368Byte
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1454 - ADAPTER PROGRAM TOOLSTICK F411336-1317 - KIT EVAL FOR C8051F411336-1314 - KIT DEV FOR C8051F41X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1309

(P1MATCH & P1MASK). This allows Software to be notified if a certain change or pattern occurs on P0 or
P1 input pins regardless of the XBRn settings. A port match event can cause an interrupt if EMAT (EIE2.1)
is set to '1' or cause the internal oscillator to awaken from SUSPEND mode. See Section “
Oscillator Suspend Mode
Bits7–0: P0.[7:0]
Bits7–0: Analog Input Configuration Bits for P0.7–P0.0 (respectively).
P0.7
R/W
R/W
Bit7
Bit7
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Port pins configured as analog inputs have their weak pullup, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input. In order for the P0.n pin to be
in analog input mode, there MUST be a '1' in the Port Latch register corresponding to
that pin.
1: Corresponding P0.n pin is not configured as an analog input.
P0.6
R/W
R/W
Bit6
Bit6
SFR Definition 18.4. P0MDIN: Port0 Input Mode
” on page
P0.5
R/W
R/W
Bit5
Bit5
SFR Definition 18.3. P0: Port0
166
P0.4
R/W
R/W
Bit4
Bit4
for more information.
Rev. 1.1
P0.3
R/W
R/W
Bit3
Bit3
P0.2
R/W
R/W
Bit2
Bit2
C8051F410/1/2/3
P0.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
P0.0
R/W
R/W
Bit0
Bit0
19.1.1. Internal
0xF1
0x80
Addressable
Reset Value
Reset Value
11111111
11111111
Bit
155