R5F21276SNFP#U0 Renesas Electronics America, R5F21276SNFP#U0 Datasheet - Page 306

• Manufacturer Part Number: R5F21276SNFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21276SNFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 32KB (32K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 25
• Ram Memory Size: 1.5KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 2.2V To 5.5V
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.20
RDRF bit in
SSSR register
RSSTP bit in
SSCRH register
RDRF bit in
SSSR register
RSSTP bit in
SSCRH register
Processing
by program
Processing
by program
Sep 26, 2008
• CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops)
• CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops)
(output)
(output)
SSCK
SSCK
SCS
SCS
SSI
SSI
Reception (4-Wire Bus Communication Mode)
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
1
0
1
0
1
0
1
0
CPHS and CPOS: Bit in SSMR register
Dummy read in
SSRDR register
Dummy read in
SSRDR register
Page 287 of 453
b7
b7
1 frame
RXI interrupt request
is generated
RXI interrupt request
is generated
1 frame
b0
Data read in SSRDR
register
Data read in SSRDR
register
b0
b7
b7
1 frame
RXI interrupt request
is generated
RXI interrupt request
is generated
1 frame
b0
b0
16. Clock Synchronous Serial Interface
Set RSSTP
bit to 1
Set RSSTP
bit to 1
b7
b7
Data read in SSRDR
register
Data read in SSRDR
register
RXI interrupt request
is generated
RXI interrupt request
is generated
High-impedance
b0
High-impedance
b0