M3087BFLGP#U3 Renesas Electronics America, M3087BFLGP#U3 Datasheet - Page 70

• Manufacturer Part Number: M3087BFLGP#U3
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 68 of 85
Figure 5.6
WR,WRL,WRH
Memory Expansion Mode and Microprocessor Mode
ADi /DBi
(when accessing an external memory space with the multiplexed bus)
ADi /DBi
Write Timing (2φ + 2φ Bus Cycle)
BCLK
BCLK
BHE
BHE
ADi
ADi
ALE
ALE
RD
CSi
CSi
Read Timing (2φ + 2φ Bus Cycle)
NOTES:
NOTES:
1. Varies with operation frequency:
1. Varies with operation frequency:
td(BCLK-ALE)
18ns.max
td(BCLK-ALE)
18ns.max
VCC1 = VCC2 = 5 V Timing Diagram (4/4)
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle aφ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle aφ + bφ, n = a)
th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle aφ + bφ, m = (b x 2) - 1)
tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle aφ + bφ, p = {(a + b - 1) x 2} + 1)
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle aφ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle aφ + bφ, n = a)
th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min
th(WR-DB) = (tcyc / 2 - 15) ns.min
td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle aφ + bφ, m = (b x 2) - 1)
tcyc=
td(BCLK-AD)
18ns.max
td(BCLK-CS)
18ns.max
td(BCLK-AD)
18ns.max
td(BCLK-CS)
18ns.max
td(AD-ALE)
td(AD-ALE)
f(BCLK)
tac2(AD-DB)
10
9
(2)
(1)
Address
Address
(1)
th(BCLK-ALE)
-2ns.min
th(BCLK-ALE)
-2ns.min
th(ALE-AD)
th(ALE-AD)
(2)
(1)
td(BCLK-RD)
18ns.max
td(BCLK-WR)
18ns.max
tdz(RD-AD)
8ns.max
Measurement Conditions:
- VCC1 = VCC2 = 4.2 to 5.5 V
- Input high and low voltage VIH = 2.5 V, VIL = 0.8 V
- Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
tac2(RD-DB)
tcyc
tcyc
td(DB-WR)
th(BCLK-WR)
-5ns.min
(1)
Data output
th(BCLK-RD)
-5ns.min
tsu(DB-BCLK) 26ns.min
th(WR-CS)
(2)
Data input
th(RD-CS)
VCC1=VCC2=5V
(2)
5. Electrical Characteristics
th(WR-DB)
th(RD-AD)
th(RD-DB) 0ns.min
(1)
th(WR-AD)
(1)
(2)
th(BCLK-AD)
-3ns.min
t
-3ns.min
Address
th(BCLK-CS)
-3ns.min
h(BCLK-CS)
Address
th(BCLK-AD)
-3ns.min
(2)