PIC10F206-I/MC Microchip Technology, PIC10F206-I/MC Datasheet - Page 4

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PIC10F206-I/MC

Manufacturer Part Number
PIC10F206-I/MC
Description
IC PIC MCU FLASH 512X12 8DFN
Manufacturer
Microchip Technology
Series
PIC® 10Fr

Specifications of PIC10F206-I/MC

Core Size
8-Bit
Program Memory Size
768B (512 x 12)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
3
Program Memory Type
FLASH
Ram Size
24 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC10
No. Of I/o's
4
Ram Memory Size
24Byte
Cpu Speed
4MHz
No. Of Timers
1
Digital Ic Case Style
DFN
Processor Series
PIC10F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
24 B
Interface Type
USB
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164334 - MODULE SOCKET FOR 8L 2X3MM DFNAC163020-2 - ADAPTER PROGRAM PIC10F 2X3 DFN
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC10F206-I/MC
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC10F200/202/204/206
3.1.2.1
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-2.
FIGURE 3-2:
3.1.2.2
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘0’s.
If the program memory is code-protected (CP = 0),
portions of the program memory will be read as zeros.
See Section 5.0 “Code Protection” for details.
FIGURE 3-3:
DS41228E-page 4
ICSPCLK
ICSPDAT
ICSPCLK
ICSPDAT
Load Data For Program Memory
Read Data From Program Memory
1
LOAD DATA COMMAND (PROGRAM/VERIFY)
READ DATA FROM PROGRAM MEMORY COMMAND
0
0
1
T
SET
2
0
1
2
1
1
T
3
SET
T
3
0
HLD
Input
1
T
1
HLD
0
4
4
0
1
x
5
5
x
Preliminary
T
X
6
6
DLY
x
T
T
1
DLY
T
DLY
DLY
2
2
1
1
strt_bit
1
strt_bit
2
2
LSb
LSb
T
3
T
SET
DLY
3
-+T
1
3
HLD
13
MSb
1
13
Output
© 2007 Microchip Technology Inc.
MSb
14
X
14
15
X
15
16
stp_bit
16
stp_bit
Input

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