PIC16C716-20I/P Microchip Technology, PIC16C716-20I/P Datasheet - Page 12

• Manufacturer Part Number: PIC16C716-20I/P
• Description: IC MCU OTP 2KX14 A/D PWM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C716-20I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 bit
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16C712/716
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1
The register file can be accessed either directly, or
indirectly through the File Select Register FSR (see
Section 2.5 “Indirect Addressing, INDF and FSR
Registers”).
DS41106B-page 10
Note 1:
RP1
= 00
= 01
= 10
= 11
(1)
Data Memory Organization
RP0
Bank 3 (not implemented)
Bank 0
Bank 1
Bank 2 (not implemented)
Maintain this bit clear to ensure upward
compatibility with future products.
GENERAL PURPOSE REGISTER
FILE
(STATUS<6:5>)
FIGURE 2-3:
Note 1: Not a physical register.
Address
File
0Ch
0Dh
1Ch
1Dh
0Ah
0Bh
0Eh
1Ah
1Bh
1Eh
0Fh
1Fh
7Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
10h
12h
13h
14h
15h
16h
17h
18h
19h
20h
11h
read as ‘0’.
Unimplemented data memory locations,
CCP1CON
DATACCP
CCPR1H
ADCON0
Registers
CCPR1L
STATUS
PCLATH
INTCON
96 Bytes
Purpose
TMR1H
General
INDF
PORTA
PORTB
T1CON
T2CON
ADRES
TMR1L
Bank 0
TMR0
TMR2
PIR1
PCL
FSR
(1)
REGISTER FILE MAP
© 2005 Microchip Technology Inc.
OPTION_REG
TRISCCP
ADCON1
Registers
PCLATH
INTCON
32 Bytes
STATUS
Purpose
General
INDF
Bank 1
TRISA
TRISB
PCON
PIE1
PCL
FSR
PR2
(1)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
FFh
Address
File