PIC16C716-20I/P Microchip Technology, PIC16C716-20I/P Datasheet - Page 43

• Manufacturer Part Number: PIC16C716-20I/P
• Description: IC MCU OTP 2KX14 A/D PWM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C716-20I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 bit
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

7.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is
either:
• driven High
• driven Low
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 7-4:
TABLE 7-2:
© 2005 Microchip Technology Inc.
Address
07h
0Bh,8Bh
0Ch
0Eh
0Fh
10h
15h
16h
17h
87h
8Ch
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
RB3/CCP1
Pin
Special Event Trigger will:
Reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion
Output Enable
TRISCCP<2>
Compare Mode
Name
DATACCP
INTCON
PIR1
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
TRISCCP
PIE1
Q
Special Event Trigger
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
R
S
CCP1CON<3:0>
Mode Select
Output
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Bit 7
GIE
—
—
—
—
—
—
(PIR1<2>)
Set flag bit CCP1IF
ADIE
Bit 6
PEIE
ADIF
match
—
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
DC1B1
CCPR1H CCPR1L
TMR1H
Bit 5
T0IE
Comparator
—
—
—
—
TMR1L
DC1B0
Bit 4
INTE
—
—
—
—
CCP1M3
Bit 3
RBIE
—
—
—
—
7.2.1
The user must configure the RB3/CCP1 pin as the CCP
output by clearing the TRISCCP<2> bit.
7.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
7.2.3
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
7.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The Special Event Trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The Special Event Trigger output of CCP1 also starts
an A/D conversion (if the A/D module is enabled).
Note:
Note:
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP1IF
CCP1IE TMR2IE
DCCP
TCCP
Bit 2
T0IF
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to
the default low level. This is neither the
PORTB I/O data latch nor the DATACCP
latch.
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The Special Event Trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR2IF
Bit 1
INTF
PIC16C712/716
—
—
TMR1IE -0-- -000 -0-- -000
TMR1IF -0-- -000 -0-- -000
DT1CK
TT1CK
RBIF
Bit 0
xxxx xxxx xxxx xuxu
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx x1x1 xxxx x1x1
Value on
POR,
BOR
DS41106B-page 41
Value on
all other
Resets