PIC16C433-I/P Microchip Technology, PIC16C433-I/P Datasheet - Page 12

• Manufacturer Part Number: PIC16C433-I/P
• Description: IC MCU CMOS 8BIT 10MHZ 2K 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C433-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• For Use With: DVA16XP185 - ADAPTER DEVICE ICE 18DIP/SOICAC164030 - MODULE SKT PROMATEII 28DIP/SOICDVA16XP140 - ADAPTER DEVICE FOR MPLAB-ICE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC16C433
3.1
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
FIGURE 3-2:
EXAMPLE 3-1:
DS41139B-page 10
1. MOVLW 55h
2. MOVWF GPIO
3. CALL
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetched
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Clocking Scheme/Instruction Cycle
OSC2/CLKOUT
INTRC modes)
(EXTRC and
SUB_1
GPIO, BIT3 (Forced NOP)
OSC1
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
PC
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch 1
Fetch INST (PC)
T
Q2
CY
0
PC
Q3
Execute 1
Fetch 2
T
CY
Q4
1
Preliminary
Q1
Execute 2
Fetch 3
T
Execute INST (PC)
CY
Fetch INST (PC+1)
Q2
2
PC+1
3.2
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (i.e., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Fetch 4
T
CY
Instruction Flow/Pipelining
Q4
3
Q1
Fetch SUB_1
Execute INST (PC+1)
Flush
T
Fetch INST (PC+2)
 2002 Microchip Technology Inc.
CY
Q2
4
PC+2
Q3
Execute SUB_1
Q4
T
CY
5
Internal
Phase
Clock