PIC16C433-I/P Microchip Technology, PIC16C433-I/P Datasheet - Page 64

• Manufacturer Part Number: PIC16C433-I/P
• Description: IC MCU CMOS 8BIT 10MHZ 2K 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C433-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• For Use With: DVA16XP185 - ADAPTER DEVICE ICE 18DIP/SOICAC164030 - MODULE SKT PROMATEII 28DIP/SOICDVA16XP140 - ADAPTER DEVICE FOR MPLAB-ICE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC16C433
9.5.1
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (see Section 7.0). The flag bit T0IF
(INTCON<2>) will be set, regardless of the state of the
enable bits. If used, this flag must be cleared in software.
9.5.2
External interrupt on GP2/INT pin is edge triggered;
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 9.8 for details on SLEEP mode.
9.5.3
An input change on GP3, GP1 or GP0 sets flag bit GPIF
(INTCON<0>). The interrupt can be enabled/disabled by
setting/clearing
(Section 5.1). This flag bit GPIF (INTCON<0>) will be
set, regardless of the state of the enable bits. If used, this
flag must be cleared in software.
EXAMPLE 9-1:
DS41139B-page 62
MOVWF
SWAPF
BCF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
RETFIE
TMR0 INTERRUPT
INT INTERRUPT
GPIO INTCON CHANGE
on
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
the
enable
SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM
(0x20 - 0x6F)
GP2/INT
bit
pin,
GPIE
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Change to bank zero, regardless of current bank
;Save status to bank zero STATUS_TEMP register
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Return from interrupt
flag
(INTCON<3>)
bit
INTF
Preliminary
9.6
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 shows the storing and restoring of the
STATUS and W registers. The register, W_TEMP, must
be defined in both banks and must be defined at the
same offset from the bank base address (i.e., if
W_TEMP is defined at 0x20 in bank 0, it must also be
defined at 0xA0 in bank 1).
Example 9.7 shows the saving and restoring of
STATUS and W using RAM locations 0x70 - 0x7F.
W_TEMP is defined at 0x70 and STATUS_TEMP is
defined at 0x71.
The example:
a)
b)
c)
d)
e)
f)
Stores the W register.
Stores the STATUS register in bank 0.
Executes the ISR code.
Restores the STATUS register (and bank select
bit).
Restores the W register.
Returns from interrupt.
Context Saving During Interrupts
 2002 Microchip Technology Inc.