Z8F6422AR020SG Zilog, Z8F6422AR020SG Datasheet - Page 148

• Manufacturer Part Number: Z8F6422AR020SG
• Description: IC ENCORE MCU FLASH 64K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F6422AR020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F642x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4283; Z8F6422AR020SG

Table 64. SPI Control Register (SPICTL)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
IRQE
7
IRQE—Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
STR—Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this
BIRQ—BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. For more information on operation of
the PHASE bit, see
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idle High (1).
WOR—Wire-OR (OPEN-DRAIN) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.
MMEN—SPI Master Mode Enable
0 = SPI configured in Slave mode.
1 = SPI configured in Master mode.
SPIEN—SPI Enable
0 = SPI disabled.
1 = SPI enabled.
bit forces the SPI to send an interrupt request to the Interrupt Control. This bit can
be used by software for a function similar to transmit buffer empty in a UART.
Writing a 1 to the IRQ bit in the SPI Status register clears this bit to 0.
STR
6
SPI Clock Phase and Polarity Control
BIRQ
5
PHASE
4
F61H
R/W
0
CLKPOL
3
Z8 Encore! XP
WOR
on page 128.
2
Product Specification
Serial Peripheral Interface
MMEN
1
®
F64XX Series
SPIEN
0
134