ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet
ST10R167-Q3
Specifications of ST10R167-Q3
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ST10R167-Q3 Summary of contents
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... DEVELOPMENT SUPPORT BUS ARBITRATION – C-COMPILERS, MACRO-ASSEMBLER PACKAGES, 144-PIN PQFP PACKAGE ROM- LESS XRAM CAN Port 6 ST10R167 16-BIT ROMLESS MCU PQFP144 ( mm) (Plastic Quad Flat Pack) OUTPUT OR SPECIAL FUNCTION EMULATORS, EVAL BOARDS, HLL-DEBUGGERS, SIMULATORS, LOGIC ANALYZER DISASSEM- BLERS, PROGRAMMING BOARDS 32 CPU-Core 16 PEC 16 ...
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... ST10R167 TABLE OF CONTENTS I INTRODUCTION ......................................................................................................... II PIN DATA .................................................................................................................. III FUNCTIONAL DESCRIPTION.................................................................................... IV MEMORY ORGANIZATION........................................................................................ V CENTRAL PROCESSING UNIT (CPU) ...................................................................... VI EXTERNAL BUS CONTROLLER............................................................................... VII INTERRUPT SYSTEM ................................................................................................ VIII CAPTURE/COMPARE (CAPCOM) UNIT ................................................................... IX GENERAL PURPOSE TIMER UNIT........................................................................... IX.1 GPT1 .......................................................................................................................... IX.2 GPT2 .......................................................................................................................... X PWM MODULE ........................................................................................................... XI PARALLEL PORTS .................................................................................................... XII A/D CONVERTER....................................................................................................... XIII SERIAL CHANNELS ...
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... XX.4.5 Oscillator watchdog (OWD) ........................................................................................ XX.4.6 Phase locked loop ...................................................................................................... XX.4.7 Memory cycle variables .............................................................................................. XX.4.8 External clock drive XTAL1 ........................................................................................ XX.4.9 Multiplexed bus ........................................................................................................... XX.4.10 Demultiplexed bus ...................................................................................................... XX.4.11 CLKOUT and READY ................................................................................................. XX.4.12 External bus arbitration ............................................................................................... XXI PACKAGE MECHANICAL DATA XXII ORDERING INFORMATION....................................................................................... ........................................................................... ST10R167 Page 3/63 ...
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... I/O capabilities. family of 16-bit It also provides on-chip high-speed RAM and clock generation via PLL ST10R167 Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit ...
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... P7.0/POUT0 20 P7.1/POUT1 21 P7.2/POUT2 22 P7.3/POUT3 23 P7.4/CC28I0 24 P7.5/CC29I0 25 P7.6/CC30I0 26 P7.7/CC31I0 27 P5.0/AN0 28 P5.1/AN1 29 P5.2/AN2 30 P5.3/AN3 31 P5.4/AN4 32 P5.5/AN5 33 P5.6/AN6 34 P5.7/AN7 35 P5.8/AN8 36 P5.9/AN9 ST10R167 ST10R167 108 P0H.0/AD8 107 P0L.7/AD7 106 P0L.6/AD6 105 P0L.5/AD5 104 P0L.4/AD4 P0L.3/AD3 103 102 P0L.2AD2 101 P0L.A/AD1 100 P0L.0/AD0 ALE 97 READY 96 WR/WRL ...
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... ST10R167 II - PIN DATA (continued) Table 1 : Pin list Symbol Pin P6 ... P8 ... 16 P7 ... 22 23 ... 26 P5 P5.10 - P5. 6/63 Type I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push/pull or open drain drivers ...
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... CAN_TxD O P4.7 A23 O External Memory Read Strobe activated for every external instruc- tion or data read access. ST10R167 Function Least Significant Segment Address Line Segment Address Line CAN Receive Data Input Segment Address Line, CAN Transmit Data Output Most Significant Segment Address Line ...
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... XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10R167. An internal pullup resistor permits power-on reset using only a capacitor connected ...
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... CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is exe- cuted, the NMI pin must be low in order to force the ST10R167 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode ...
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... ROMLESS 2K Byte XRAM CAN_RXD CAN CAN_TXD 16 External Memory 16 8 Port 6 8 10/63 block diagram gives an overview of the different on-chip components and the high bandwidth inter- nal bus structure of the ST10R167. 32 CPU-Core 16 16 Interrupt Controller BRG BRG Port 5 Port Internal 16 RAM Watchdog PEC OSC ...
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... The XRAM address range is 00’E000h - 00’E7FFh if the XRAM is enabled (XPEN bit 2 of SYSCON register). As the XRAM appears like external memory, it cannot be used for the ST10R167’s system stack or register banks. The ST10R167 is XRAM is not provided for single bit storage and therefore is not bit addressable ...
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... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10R167’s instructions can be exe- cuted in one instruction cycle which requires 80ns at 25MHz CPU clock. For example, shift and rotate instructions are processed in one instruc- tion cycle independent of the number of bits to be shifted ...
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... The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. ST10R167 13/63 ...
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... Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individ- ual trap (interrupt) number. Table 2 shows all the available ST10R167 inter- rupt sources and the corresponding hard- ware-related locations and trap (interrupt) numbers : Request ...
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... SCRIE SCRINT SCEIR SCEIE SCEINT PWMIR PWMIE PWMINT XP0IR XP0IE XP0INT XP1IR XP1IE XP1INT XP2IR XP2IE XP2INT XP3IR XP3IE XP3INT ST10R167 Vector Trap Location Number 00’00C8h 00’00CCh 00’00D0h 00’00D4h 00’00D8h 00’00DCh 00’00E0h 00’00E4h 00’00E8h 00’00ECh 00’00E0h 00’0110h 00’0114h 00’0118h T0INT 00’0080h T1INT 00’ ...
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... ST10R167 VII - INTERRUPT SYSTEM (continued) Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a stan- dard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag regis- ...
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... VIII - CAPTURE/COMPARE (CAPCOM) UNIT The ST10R167 has two 16 channel CAPCOM units. They support generation and control of timing sequences channels with a maximum resolution of 320ns at 25MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation ...
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... ST10R167 IX - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2 ...
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... Table 7 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode. ST10R167 U/D Interrupt Request T3OUT T3OTL Interrupt ...
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... ST10R167 IX - GENERAL PURPOSE TIMER UNIT (continued) Table 7 : GPT2 timer input frequencies, resolution and periods f = 25MHz CPU 000B Pre-scaler factor 4 Input Frequency 6.25MHz 3.125MHz 1.563MHz Resolution 160ns Period 10.49ms Figure 6 : Block diagram of GPT2 T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock ...
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... Hz 47.68Hz * PPx Period Register Match Comparator * PTx 16-Bit Up/Down Counter Match Comparator Shadow Register * PWx Pulse Width Register ST10R167 14-bit 16-bit 1.526KHz 0.381KHz 23.84Hz 5.96Hz 14-bit 16-bit 762.9Hz 190.7Hz 11.92Hz 2.98Hz Up/Down/ Clear Control Output Control POUTx ...
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... ST10R167 XI - PARALLEL PORTS The ST10R167 provides up to 111 I/O lines orga- nized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/out- put lines are individually (bit-wise) programmable as input or output via direction registers. The I/O ...
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... One calibration cycle is performed after each conversion : each calibration cycle takes 4 ADC clock cycles. These operation cycles ensure constant updating of the ADC accuracy, com- pensating changing operating conditions. CC ADSTC 25MHz CPU ST10R167 injection mode : when + Sample Clock 25MHz - CPU t 0. ...
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... ST10R167 XIII - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral com- ponents is provided by two serial interfaces: the asynchronous/synchronous (ASC0) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning ...
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... High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible communication between the ST10R167 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode received from an external master (slave mode) ...
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... ST10R167 XIV - CAN MODULE The integrated CAN module handles the com- pletely autonomous transmission and reception of CAN frames in accordance with the CAN specifi- cation V2.0 part B (active) i.e. the on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers ...
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... XVI - INSTRUCTION SET SUMMARY The table below lists the instructions of the ST10R167. The various addressing modes, instruction operation, parameters for conditional Table 13 : Instruction set summary Mnemonic ADD(B) Add Word (Byte) operands ADDC(B) Add Word (Byte) operands with Carry SUB(B) Subtract Word (Byte) operands ...
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... ST10R167 XVI - INSTRUCTION SET SUMMARY (continued) Table 13 : Instruction set summary (continued) Mnemonic JNBS Jump relative and set bit if direct bit is not set CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met CALLS Call absolute subroutine in any code segment PCALL Push direct Word register onto system stack & call absolute subroutine ...
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... This means that the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 TCL. The consequence is that during a watchdog timer reset or software reset, the behavior of the ST10R167 is equal to an external hardware reset. ST10R167 instruction can ...
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... ST10R167 XVIII - POWER REDUCTION MODES Two different power reduction modes with differ- ent levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped ...
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... XIX - SPECIAL FUNCTION REGISTER OVERVIEW Table 14 lists all SFRs which are implemented in the ST10R167 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. ...
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... ST10R167 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued) Physical Name address CC8IC b FF88h CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC b FF8Eh CC12 FE98h CC12IC b FF90h CC13 FE9Ah CC13IC b FF92h CC14 FE9Ch ...
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... CPU Data Page Pointer 2 Register (10 bit) 03h CPU Data Page Pointer 3 Register (10 bit) E0h External Interrupt Control Register 3Eh Device Identifier Register 3Fh Manufacturer Identifier Register 3Dh On-chip Memory Identifier Register ST10R167 Description Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...
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... ST10R167 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued) Physical Name address IDPROG F078h E MDC b FF0Eh MDH FE0Ch MDL FE0Eh ODP2 b F1C2h E ODP3 b F1C6h E ODP6 b F1CEh E ODP7 b F1D2h E ODP8 b F1D6h E ONES FF1Eh P0L b FF00h P0H b FF02h ...
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... CAPCOM Timer 0 Interrupt Control Register 2Ah CAPCOM Timer 0 Reload Register 29h CAPCOM Timer 1 Register CFh CAPCOM Timer 1 Interrupt Control Register 2Bh CAPCOM Timer 1 Reload Register 20h GPT1 Timer 2 Register ST10R167 Description Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...
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... ST10R167 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued) Physical Name address T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h T5IC b FF66h T6 FE48h T6CON b FF48h T6IC b FF68h ...
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... ESFR Description IDMANUF : Manufacturer Identifier - 0400h: STmicroelectronics Manufacturer (JTAG world- wide normalisation). IDCHIP (F07Ch / 3Eh) ESFR Description IDCHIP: Device Identifier - 0A72h for ST10R167. IDMEM (F07Ah / 3Dh) ESFR Description IDMEM: 1008h for ST10R167 (Romless MCU). IDPROG (F078h / 3Ch) ESFR Description IDPROG: 0000h for ST10R167 (Romless MCU). ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS XX.1 - Absolute maximum ratings Symbol V Voltage on V pins with respect to ground Voltage on any pin with respect to ground SS Input current on any pin during overload condition Absolute sum of all input currents during overload condition P Power Dissipation tot T Ambient Temperature under bias ...
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... V – ±0.5 DD < V – ±1 DD – ±5 50 250 – -40 -500 – OLmax 40 – OLmax – 500 – -40 -500 – – -10 -100 – < V – ±20 DD – IH1 CPU 6 – IH1 6 7 100 400 ST10R167 Unit – 0 CPU mA CPU A 39/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) Notes 1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2. The maximum current may be drawn while the respective signal line remains inactive. ...
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... Test Points 0.2V 0.2V -0 Timing Reference Points After the end of the sample time t S depend on programming and can be taken SC specification) occurs on maximum The maximum internal resistance results CC Sample clock +0 -0. +0.1V OL changes of ±100mV. LOAD /V level occurs ( 20mA ST10R167 , changes of the 41/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.1 - Definition of internal timing The internal operation of the ST10C167 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “ ...
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... CPU individual TCLs. The timings listed in the AC Characteristics that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances. ST10R167 CPU XTAL is constantly adjusted CPU . The slight variation causes a jitter XTAL which also effects the duration of ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes F locked The relative deviation of TCL is XTAL the maximum when it is refered to one TCL period. It decreases according to the formula and to the Figure 12 given below. For N periods of ...
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... Max. Min. Max. 2 500 100 * N 20 – – – 3 – – 3 – OSC Variable CPU Clock 1/2TCL = 1 to 25MHz Min. Max. – TCL - – TCL - 16 – TCL - – TCL - – - ST10R167 * N Unit ns – ns – Unit – ns – ns – ns – ns – ns 45/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) Table 18 : Multiplexed bus characteristics (continued) Symbol Parameter 1 CC Address float after RD (with RW-delay Address float after RD RW-delay RD, WR low time (with RW-delay RD, WR low time (no RW-delay valid data in (with 14 RW-delay valid data in (no RW-delay ALE low to valid data in ...
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... Note 1. Guaranteed by design characterization. Max. CPU Clock Variable CPU Clock = 25MHz 1/2TCL = 1 to 25MHz Min. Max. Min – 2TCL - – 3TCL - – 2TCL - 14 – 0 – – – 2TCL - – 2TCL - ST10R167 Unit Max. – – – – ns 2TCL - – – 47/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 14 : External Memory Cycle : multiplexed bus, with/without read/write delay, normal ALE CLKOUT t ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle BUS (P0) RD Write Cycle BUS (P0) WR WRL WRH 48/ Address Address Address Address Data Data Out ...
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... XX - ELECTRICAL CHARACTERISTICS (continued) Figure 15 : External Memory Cycle: multiplexed bus, with/without read/write delay, extended ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 BUS (P0) RD Write Cycle BUS (P0) WR WRL WRH Address t 7 Address Address ST10R167 Data Data Out 49/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 16 : External Memory Cycle: multiplexed bus, with/without read/write delay, normal ALE, read/ write chip select CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle BUS (P0) RdCSx Write Cycle BUS (P0) WrCSx 50/ Address Address Address Address Data Data Out ...
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... XX - ELECTRICAL CHARACTERISTICS (continued) Figure 17 : External Memory Cycle: multiplexed bus, with/without read/write delay, extended ALE, read/ write chip select CLKOUT t ALE t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 BUS (P0) RdCSx Write Cycle BUS (P0) WrCSx Address t 7 Address Address Data Data Out ST10R167 51/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.10 - Demultiplexed bus ± (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF (for Port 6, CS) = 100pF L ALE cycle time = 4 TCL + 2t A Table 19 : Demultiplexed bus characteristics Symbol Parameter t CC ALE high time Address setup to ALE ALE falling edge to RD, WR (with ...
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... Min. Max. Min – – – C – – – 2TCL - – 3TCL - – 2TCL - – 0 – – F – – – - – TCL - ST10R167 Unit Max. – 2TCL - 3TCL - – – – – ns 2TCL - TCL - – – 53/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 18 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ALE CLKOUT ALE CSx A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RD Write Cycle Data Bus (P0) WR WRL WRH 54/ Address Data Out 41u Data ...
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... XX - ELECTRICAL CHARACTERISTICS (continued) Figure 19 : External Memory Cycle: demultiplexed bus, with/without read/write delay, extended ALE CLKOUT t ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RD Write Cycle Data Bus (P0) WR WRL WRH Address Data Data Out ST10R167 55/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 20 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ALE, read/ write chip select CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RdCsx Write Cycle Data Bus (P0) WrCSx 56/ Address Data Out Data ...
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... XX - ELECTRICAL CHARACTERISTICS (continued) Figure 21 : External Memory Cycle: demultiplexed bus, with/without read/write delay, extended ALE, read/write chip select CLKOUT t ALE A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RdCsx Write Cycle Data Bus (P0) WrCSx Address Data Data Out ST10R167 57/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.11 - CLKOUT and READY ± (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF L C (for Port 6, CS) = 100pF L Table 20 : CLKOUT and READY characteristics Symbol Parameter t CC CLKOUT cycle time CLKOUT high time CLKOUT low time ...
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... For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7. The next external bus cycle may start here. READY Running cycle 1) waitstate order to be safely synchronized. This is guaranteed, if READY is removed in response 37 ST10R167 MUX/Tristate 59/63 ...
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... ST10R167 XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.12 - External bus arbitration ± (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF L C (for Port 6, CS) = 100pF L Table 21 : External bus arbitration Symbol Parameter SR HOLD input setup time to CLKOUT CLKOUT to HLDA hig or BREQ low delay ...
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... Notes 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10C167 requesting the bus. 2. The next ST10C167 driven bus cycle may start here ST10R167 t 65 61/63 ...
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... ST10R167 XXI - PACKAGE MECHANICAL DATA Figure 25 : Package Outline PQFP144 (28 x 28mm) 144 Dimensions Minimum A A1 0.25 A2 3.17 B 0.22 c 0.13 D 30.95 D1 27. 30.95 E1 27. Note 1. Package dimensions are in mm. The dimensions quoted in inches are rounded. XXII - ORDERING INFORMATION Salestype 1 ST10C167-Q3/XX 1 ST10C167-Q6/XX ...
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... The ST logo is a registered trademark of STMicroelectronics Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. © 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES http://www.st.com ST10R167 63/63 ...