ST10R272LT6 STMicroelectronics, ST10R272LT6 Datasheet
ST10R272LT6
Specifications of ST10R272LT6
Available stocks
Related parts for ST10R272LT6
ST10R272LT6 Summary of contents
Page 1
LOW VOLTAGE ROMLESS MCU WITH MAC High Performance 16-bit CPU CPU Frequency MHz 40ns instruction cycle time at 50-MHz CPU clock Multiply-Accumulate unit (MAC) 4-stage pipeline Register-based design with multiple variable register banks Enhanced boolean bit ...
Page 2
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
P4.3/A19 P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK RD W R/W RL READY/READY ALE RPD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P7.3/POUT3 P7.2 P7.1 P7.0 ...
Page 5
P5.10 98-100 I –P5. 100 XTAL1 5 I XTAL2 6-bit input-only port with Schmitt-Trigger characteristics. Port 5 pins also serve as timer inputs: ...
Page 6
ST10R272L - PIN DESCRIPTION P3.0 – 8-21 I/O P3.13 P3. 15-bit ...
Page 7
P4.0– 23-26 I/O P4.7 29-32 ... ... I WR WRL READY READY 5T An 8-bit bidirectional I/O port. ...
Page 8
ST10R272L - PIN DESCRIPTION ALE PORT0: I/O P0L.0– P0L.7, P0H P0H.7 PORT1: I/O P1L.0– 59- 66 P1L.7, P1H.0 - 67, 68 P1H.7 71-76 8/ Address Latch ...
Page 9
RSTIN RSTOUT NMI 81 I P6.0- 82-89 I/O P6 ... ... I Reset Input with Schmitt-Trigger characteristics. Resets the device when a low level is applied ...
Page 10
ST10R272L - PIN DESCRIPTION P2.8 – I/O P2. ... ... 93 I P7.0 – I/O P7 RPD 38, 49, 69 ...
Page 11
FUNCTIONAL DESCRIPTION ST10R272L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different on- chip components and the internal bus structure. EA, ALE, RD, WR/WRL, READY, NMI, ...
Page 12
ST10R272L - MEMORY MAPPING 3 MEMORY MAPPING The ST10R272L is a ROMless device, the internal RAM space is 1 KByte. The RAM address space is used for variables, register banks, the system stack, the PEC pointers (in 00’FCE0h - 00’FCFFh) ...
Page 13
CENTRAL PROCESSING UNIT The main core of the CPU contains a 4-stage instruction pipeline, a MAC multiply- accumulation unit, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most instructions can be executed in one ...
Page 14
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) 5 MULTIPLY-ACCUMULATE UNIT (MAC) The MAC is a specialized co-processor added to the ST10R272L CPU core to improve the performance of signal processing algorithms. It includes: • a multiply-accumulate unit • an address generation unit, ...
Page 15
MAC Features Enhanced addressing capabilities • Double indirect addressing mode with pointer post-modification. • Parallel Data Move allows one operand move during Multiply-Accumulate instructions without penalty. • CoSTORE instruction (for fast access to the MAC SFRs) and CoMOV (for ...
Page 16
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) 5.2 MAC Operation Instruction pipelining All MAC instructions use the 4-stage pipeline. During each stage the following tasks are performed: • FETCH: All new instructions are double-word instructions. • DECODE: If required, operand addresses are ...
Page 17
The following table shows the various combinations of pointer post-modification for each of these 2 new addressing modes. In this document the symbols “[Rw these addressing modes. Symbol “[IDX i ]” stands for “[Rw ]” stands for n Table 2 ...
Page 18
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) The Parallel Data Move shifts a table of operands in parallel with a computation on those operands. Its specific use is for signal processing algorithms like filter computation. The following figure gives an example of ...
Page 19
B-source and A- source, respectively, to the Accumulator (case of Multiplication, Shift.). The output of the arithmetic unit goes to the Accumulator also possible to saturate the ...
Page 20
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Accumulator shifter The Accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The source operand of the shifter is the Accumulator and the possible shifting operations are: • No shift ...
Page 21
If the Repeat Unit is used in the interrupt routine, MRW must be saved by the user and restored before the end of the interrupt routine. Note The Repeat Count should be ...
Page 22
ST10R272L - INTERRUPT AND TRAP FUNCTIONS Number representation & rounding The MAC supports the two’s-complement representation of binary numbers. In this format, the sign bit is the MSB of the binary word. This is set to zero for positive numbers ...
Page 23
Interrupt Sources Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register ...
Page 24
ST10R272L - INTERRUPT AND TRAP FUNCTIONS 6.2 Hardware Traps Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table ...
Page 25
PARALLEL PORTS The ST10R272L provides I/O lines organized into 7 input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. ...
Page 26
ST10R272L - PWM MODULE of external memory space, the address space can be restricted to 1 MByte, 256 KByte KByte. 9 PWM MODULE A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width ...
Page 27
GENERAL PURPOSE TIMERS The GPTs are flexible multifunctional timer/counters used for time-related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit contains five 16-bit timers, organized in ...
Page 28
ST10R272L - GENERAL PURPOSE TIMERS Timer input selection F =50MHz CPU 000b 001b Prescaler 8 16 Factor Input 6.25 MHz 3.125 Frequency MHz Resolution 160ns 320ns Period 10.49ms 20.97ms Table 8 GPT1 timer input frequencies, resolution and periods T2E UD ...
Page 29
GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock derived from the CPU clock via a programmable ...
Page 30
ST10R272L - SERIAL CHANNELS T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock n 2 n=2...9 T6EUD 11 SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with ...
Page 31
S0BRS = ‘0’ 50MHz CPU Baud Rate Deviation Error (Baud) 1562500 0.0% / 0.0% 56000 +3.3% / -0.4% ...
Page 32
ST10R272L - WATCHDOG TIMER SSPCKS Value 011 SSP clock = CPU clock divided by 16 100 SSP clock = CPU clock divided by 32 101 SSP clock = CPU clock divided by 64 110 SSP clock = CPU clock divided ...
Page 33
SYSTEM RESET The following type of reset are implemented on the ST10R272L: Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock signal on XTAL1 not internally resynchronized, it resets the microcontroller into its default ...
Page 34
ST10R272L - POWER REDUCTION MODES 14 POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle ...
Page 35
Physical Name Address CC9IC b FF8Ah CC10IC b FF8Ch CC11IC b FF8Eh CP FE10h CRIC b FF6Ah CSP FE08h DP0L b F100h E DP0H b F102h E DP1L b F104h E DP1H b F106h E DP2 b FFC2h DP3 b ...
Page 36
ST10R272L - SPECIAL FUNCTION REGISTERS Physical Name Address IDX1 b FF0Ah MAH FE5Eh MAL FE5Ch MCW FFDCh MDC b FF0Eh MDH FE0Ch MDL FE0Eh MRW b FFDAh MSW b FFDEh ODP2 b F1C2h E ODP3 b F1C6h E ODP6 b ...
Page 37
Physical Name Address PECC2 FEC4h PECC3 FEC6h PECC4 FEC8h PECC5 FECAh PECC6 FECCh PECC7 FECEh PP3 F03Eh E PSW b FF10h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E QR0 F004h E QR1 F006h E QX0 ...
Page 38
ST10R272L - SPECIAL FUNCTION REGISTERS Physical Name Address SP FE12h SSPCON0 EF00h X SSPCON1 EF02h X SSPRTB EF04h X SSPTBH EF06h X STKOV FE14h STKUN FE16h SYSCON b FF12h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON ...
Page 39
Physical Name Address XP1IC b F18Eh E XP3IC b F19Eh E ZEROS b FF1Ch Note 1. The system configuration is selected during reset. Note 2. Bit WDTR indicates a watchdog timer triggered reset. ST10R272L - SPECIAL FUNCTION REGISTERS 8-Bit Description ...
Page 40
ST10R272L - ELECTRICAL CHARACTERISTICS 16 ELECTRICAL CHARACTERISTICS 16.1 Absolute Maximum Ratings • Ambient temperature under bias ( T • Storage temperature ( T • Voltage on V pins with respect to ground ( V DD • Voltage on any pin ...
Page 41
Remarks on 5 volt tolerant (5T) and 5 volt fail-safe (5S) pins The 5V tolerant input and output pins can sustain an absolute maximum external voltage of 5.5V. However, signals on unterminated bus lines might have overshoot above 5.5V, presenting ...
Page 42
ST10R272L - ELECTRICAL CHARACTERISTICS 16.2 DC Characteristics V = 3.3V 0. Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN, RPD Input high voltage XTAL1 Output low voltage (ALE, RD, ...
Page 43
Parameter 3 PORT0 configuration current 2 RPD pulldown current XTAL1 input current 6) Pin capacitance (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current 1) This specification is not valid for outputs which are switched to ...
Page 44
ST10R272L - ELECTRICAL CHARACTERISTICS 200 150 100 15 10 Figure 10 Supply/idle current vs operating frequency 44/ CCmax I IDmax 50 f [MHz] CPU ...
Page 45
AC Characteristics Test conditions • Input pulse levels: ........................................................................................... 0 to +3.0 V • Input rise and fall times (10%-90%):........................................................................ 2.5 ns • Input timing reference levels: ................................................................................. +1.5 V • Output timing reference levels: .............................................................................. +1.5 V • ...
Page 46
ST10R272L - ELECTRICAL CHARACTERISTICS From output under test LOAD V OL For timing purposes a port pin is no longer floating when a 150 mV change from load voltage occurs, but begins to float when a 150 ...
Page 47
CPU Clock Generation Mechanisms ST10R272L internal operation is controlled by the CPU clock f clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external timing (AC Characteristics) specification therefore depends on the time between two ...
Page 48
ST10R272L - ELECTRICAL CHARACTERISTICS P0.15-13 (P0H.7- Table 15 CPU clock generation mechanisms 1) The maximum depends on the duty cycle of the external clock signal. ...
Page 49
Note The address float timings in Multiplexed bus mode (t TCL = 1 f max XTAL Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for ...
Page 50
ST10R272L - ELECTRICAL CHARACTERISTICS where N = number of consecutive TCLs and 1 and 3TCL min PLL jitter is an important factor for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For slower operations and ...
Page 51
Memory Cycle Variables The timing tables below use three variables derived from the BUSCONx registers and represent programmed memory cycle characteristics. Table 16 describes how these variables are computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time ...
Page 52
ST10R272L - ELECTRICAL CHARACTERISTICS 16.3.3 Multiplexed Bus 3 ALE cycle time = 6 TCL + 2 A Parameter Symbol ALE high time t 5 Address (P1, P4), BHE t 6 setup ...
Page 53
Parameter Symbol Data hold after rising edge Data float after RD rising t 19 12)) edge t Data valid Data hold after ALE rising edge after RD Address ...
Page 54
ST10R272L - ELECTRICAL CHARACTERISTICS Parameter Symbol RdCS to Valid Data (with RW delay) RdCS to Valid Data (no RW delay) RdCS, WrCS Low Time t 48 (with RW delay) RdCS, WrCS Low Time t ...
Page 55
CLKOUT t 5 ALE t 38u CSx t 6 A23-A16 (A15-A8) BHE t 6m Read Cycle BUS P0 RD Write Cycle BUS P0 WR, WRL, WRH Figure 16 External memory cycle: multiplexed bus, with/without read/write delay, normal ALE ST10R272L - ...
Page 56
ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT t 5 ALE t 38u CSx t 6d/b A23-A16 (A15-A8) BHE Read Cycle t 6m BUS P0 RD Write Cycle BUS P0 WR WRL, WRH multiplexed bus, with/without read/write delay, extended ALE 56/ ...
Page 57
CLKOUT t 5 ALE t 6b/d A23-A16 (A15-A8) BHE t 6m Read Cycle BUS P0 RdCSx Write Cycle BUS P0 WrCSx multiplexed bus, with/without read/write delay, normal ALE, read/write chip select ST10R272L - ELECTRICAL CHARACTERISTICS Address ...
Page 58
ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT t ALE t 6d/b A23-A16 (A15-A8) BHE Read Cycle t BUS P0 RdCSx Write Cycle BUS P0 WR WRL, WRH multiplexed bus, with/without read/write delay, extended ale, read/write chip select 58/ ...
Page 59
Demultiplexed Bus 3 ALE cycle time = 4 TCL + 2 A Parameter ALE high time Address (P1, P4), BHE setup to ALE Address setup to RD, WR (with RW-delay) ...
Page 60
ST10R272L - ELECTRICAL CHARACTERISTICS Parameter Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR Address hold after WRH Latched CS setup to ALE Unlatched CS setup to ALE Latched CS low to Valid Data ...
Page 61
Parameter Symbol Data hold after RdCS t Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after t RdCS, WrCS Data hold after WrCS t 1) Output loading is ...
Page 62
ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT ALE CSx A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RD Write Cycle P0 BUS (D15-D8) D7-D0 WR(L), WRH demultiplexed bus, with/without read/write delay, normal ALE 62/ 38u ...
Page 63
CLKOUT t 5 ALE t 38u CSx t A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RD Write Cycle P0 BUS (D15-D8) D7-D0 WR(L), WRH demultiplexed bus, with/without read/write delay, extended ALE ST10R272L - ELECTRICAL CHARACTERISTICS ...
Page 64
ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RdCsx Write Cycle P0 BUS (D15-D8) D7-D0 WrCSx demultiplexed bus, with/without read/write delay, normal ALE, read/write chip select 64/ ...
Page 65
CLKOUT t 5 ALE t A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RdCSx Write Cycle P0 BUS (D15-D8) D7-D0 WrCSx demultiplexed bus, no read/write delay, extended ALE, read/write chip select ST10R272L - ELECTRICAL CHARACTERISTICS ...
Page 66
ST10R272L - ELECTRICAL CHARACTERISTICS 16.3.5 CLKOUT and READY/READY 3 Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time 1) CLKOUT rise time 1 CLKOUT fall time CLKOUT rising edge to ALE ...
Page 67
CLKOUT ALE Command RD, WR Sync READY t 58 Async 3) READY Sync READY t 58 Async 3) READY Figure 24 CLKOUT and READY/READY 1 Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2 The ...
Page 68
ST10R272L - ELECTRICAL CHARACTERISTICS 6 Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for ...
Page 69
External Bus Arbitration 3 Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive ...
Page 70
ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT t 61 HOLD HLDA 1) BREQ CSx (On P6.x) Other Signals Figure 25 External bus arbitration, releasing the bus 1 The ST10R272L will complete the running bus cycle before granting bus access. 2 This is ...
Page 71
CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Figure 26 External bus arbitration, (regaining the bus) 1 This is the last chance for BREQ to trigger the regain-sequence indicated. Even if BREQ is activated earlier, the regain-sequence ...
Page 72
ST10R272L - ELECTRICAL CHARACTERISTICS 16.3.7 External Hardware Reset = 3 Parameter Symbol 1) t Sync. RSTIN low time 70 RSTIN low to internal t 71 reset sequence start internal reset sequence (RSTIN internally ...
Page 73
RSTIN Internal Reset Signal ALE RD PORT0 PORT1 (Demux Bus) 5) RSTOUT 6) Other IOs t 77 Figure 27 External asynchronous hardware reset (power-up reset): Vpp low 1 The ST10R272L is reset in its default state asynchronously ...
Page 74
ST10R272L - ELECTRICAL CHARACTERISTICS . t 70 RSTIN t 711) Internal Reset Signal ALE RD PORT0 PORT1 (Demux Bus) 6) RSTOUT 7) Other IOs t 77 Figure 28 External synchronous hardware reset (warm reset): Vpp high 1 The ...
Page 75
Synchronous Serial Port Timing = 3 Parameter SSP clock cycle time SSP clock high time SSP clock low time SSP clock rise time SSP clock fall time CE active before shift edge ...
Page 76
ST10R272L - ELECTRICAL CHARACTERISTICS 1) SSPCLK t 205 SSPCEx t 207 SSPDAT 1) SSPCLK SSPCEx SSPDAT last Wr. Bit 1 The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge ...
Page 77
... ORDERING INFORMATION Sales type ST10R272LT1 ST10R272LT6 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...