C8051T603-GS Silicon Laboratories Inc, C8051T603-GS Datasheet - Page 96

• Manufacturer Part Number: C8051T603-GS
• Description: IC 8051 MCU 4K-EEPROM 14-SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T60xr

Specifications of C8051T603-GS

• Program Memory Type: OTP
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T600DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1404 - KIT DEV FOR C8051T60X MCU'S
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1657-5

C8051T600/1/2/3/4/5/6
SFR Definition 19.1. RSTSRC: Reset Source
SFR Address = 0xEF
96
Note: Do not use read-modify-write operations on this register
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
MEMERR EPROM Error Reset Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
C0RSEF Comparator0 Reset Enable
SWRSF
PINRSF
Unused
PORSF
Name
R
7
0
Unused.
and Flag.
Software Reset Force and
Flag.
Enable and Flag.
Power-On/V
Reset Flag, and V
Reset Enable.
HW Pin Reset Flag.
MEMERR
Varies
R
6
Description
DD
C0RSEF
Monitor
Varies
R/W
DD
5
monitor
SWRSF
Varies
R/W
Rev. 1.2
4
Don’t care.
N/A
Writing a 1 enables
Comparator0 as a reset
source (active-low).
Writing a 1 forces a sys-
tem reset.
Writing a 1 enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Writing a 1 enables the
V
ures it as a reset source.
Writing 1 to this bit while
the V
abled may cause a sys-
tem reset.
N/A
DD
monitor and config-
DD
WDTRSF
monitor is dis-
Varies
Write
R
3
MCDRSF
Varies
R/W
2
0
Set to 1 if EPROM
read/write error caused
the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 any time a power-
on or V
occurs.
When set to 1, all other
RSTSRC flags are inde-
terminate.
Set to 1 if RST pin caused
the last reset.
PORSF
Varies
R/W
DD
1
Read
monitor reset
PINRSF
Varies
R
0