C8051F817-GS Silicon Laboratories Inc, C8051F817-GS Datasheet - Page 229

• Manufacturer Part Number: C8051F817-GS
• Description: IC MCU 8BIT 8K FLASH 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F81xr

Specifications of C8051F817-GS

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Processor Series: C8051F8x
• Core: 8051
• Data Bus Width: 16 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F800DK
• Minimum Operating Temperature: - 55 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1792-5

29.3.1. Edge-Triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun-
ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
Port I/O
hardware.
Crossbar
CEXn
Figure 29.4. PCA Capture Mode Diagram
W
M
P
1
6
n
x
PCA0CPMn
E
C
O
M
n
x
C
A
P
P
n
Rev. 1.0
C
A
P
N
n
0
1
M
A
T
n
0 0 0 x
O
G
T
n
W
M
P
n
E
C
C
F
n
0
1
C
F
C
R
PCA0CN
PCA
Timebase
C
C
F
2
C
C
F
1
C8051F80x-83x
C
C
F
0
PCA Interrupt
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H
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